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https://github.com/RPCS3/llvm.git
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[SPARCv9] Add support for the rdpr/wrpr instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249262 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger
parent
295b19789d
commit
58b865b86c
@ -1024,6 +1024,82 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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RegKind = SparcOperand::rk_IntReg;
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return true;
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}
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if (name.equals("tpc")) {
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RegNo = Sparc::TPC;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tnpc")) {
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RegNo = Sparc::TNPC;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tstate")) {
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RegNo = Sparc::TSTATE;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tt")) {
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RegNo = Sparc::TT;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tick")) {
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RegNo = Sparc::TICK;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tba")) {
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RegNo = Sparc::TBA;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("pstate")) {
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RegNo = Sparc::PSTATE;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tl")) {
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RegNo = Sparc::TL;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("pil")) {
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RegNo = Sparc::PIL;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("cwp")) {
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RegNo = Sparc::CWP;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("cansave")) {
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RegNo = Sparc::CANSAVE;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("canrestore")) {
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RegNo = Sparc::CANRESTORE;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("cleanwin")) {
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RegNo = Sparc::CLEANWIN;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("otherwin")) {
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RegNo = Sparc::OTHERWIN;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("wstate")) {
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RegNo = Sparc::WSTATE;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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}
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return false;
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}
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@ -117,6 +117,12 @@ static const unsigned ASRRegDecoderTable[] = {
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SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
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SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
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static const unsigned PRRegDecoderTable[] = {
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SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
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SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
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SP::OTHERWIN, SP::WSTATE
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};
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static const uint16_t IntPairDecoderTable[] = {
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SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
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SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
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@ -203,6 +209,15 @@ static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= array_lengthof(PRRegDecoderTable))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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@ -1327,6 +1327,25 @@ let hasSideEffects = 1 in {
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}
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}
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// Section A.43 - Read Privileged Register Instructions
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let Predicates = [HasV9] in {
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let rs2 = 0 in
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def RDPR : F3_1<2, 0b101010,
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(outs IntRegs:$rd), (ins PRRegs:$rs1),
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"rdpr $rs1, $rd", []>;
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}
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// Section A.62 - Write Privileged Register Instructions
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let Predicates = [HasV9] in {
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def WRPRrr : F3_1<2, 0b110010,
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(outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wrpr $rs1, $rs2, $rd", []>;
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def WRPRri : F3_2<2, 0b110010,
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(outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wrpr $rs1, $simm13, $rd", []>;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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@ -102,6 +102,22 @@ def PSR : SparcCtrlReg<0, "PSR">;
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def WIM : SparcCtrlReg<0, "WIM">;
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def TBR : SparcCtrlReg<0, "TBR">;
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def TPC : SparcCtrlReg<0, "TPC">;
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def TNPC : SparcCtrlReg<1, "TNPC">;
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def TSTATE : SparcCtrlReg<2, "TSTATE">;
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def TT : SparcCtrlReg<3, "TT">;
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def TICK : SparcCtrlReg<4, "TICK">;
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def TBA : SparcCtrlReg<5, "TBA">;
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def PSTATE : SparcCtrlReg<6, "PSTATE">;
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def TL : SparcCtrlReg<7, "TL">;
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def PIL : SparcCtrlReg<8, "PIL">;
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def CWP : SparcCtrlReg<9, "CWP">;
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def CANSAVE : SparcCtrlReg<10, "CANSAVE">;
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def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">;
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def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">;
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def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
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def WSTATE : SparcCtrlReg<14, "WSTATE">;
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// Integer registers
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def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
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def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
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@ -285,3 +301,8 @@ def ASRRegs : RegisterClass<"SP", [i32], 32,
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(add Y, (sequence "ASR%u", 1, 31))> {
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let isAllocatable = 0;
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}
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// Privileged Registers
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def PRRegs : RegisterClass<"SP", [i64], 64,
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(add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
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CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;
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@ -110,3 +110,186 @@
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! V8-NEXT: stx %fsr,[%g2 + %i5]
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! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
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stx %fsr,[%g2 + %i5]
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tpc
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! V9: wrpr %g6, %fp, %tpc ! encoding: [0x81,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tpc
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tnpc
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! V9: wrpr %g6, %fp, %tnpc ! encoding: [0x83,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tnpc
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tstate
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! V9: wrpr %g6, %fp, %tstate ! encoding: [0x85,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tt
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! V9: wrpr %g6, %fp, %tt ! encoding: [0x87,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tt
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tick
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! V9: wrpr %g6, %fp, %tick ! encoding: [0x89,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tick
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tba
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! V9: wrpr %g6, %fp, %tba ! encoding: [0x8b,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tba
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%pstate
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! V9: wrpr %g6, %fp, %pstate ! encoding: [0x8d,0x91,0x80,0x1e]
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wrpr %g6,%i6,%pstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%tl
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! V9: wrpr %g6, %fp, %tl ! encoding: [0x8f,0x91,0x80,0x1e]
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wrpr %g6,%i6,%tl
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%pil
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! V9: wrpr %g6, %fp, %pil ! encoding: [0x91,0x91,0x80,0x1e]
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wrpr %g6,%i6,%pil
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%cwp
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! V9: wrpr %g6, %fp, %cwp ! encoding: [0x93,0x91,0x80,0x1e]
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wrpr %g6,%i6,%cwp
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%cansave
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! V9: wrpr %g6, %fp, %cansave ! encoding: [0x95,0x91,0x80,0x1e]
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wrpr %g6,%i6,%cansave
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%canrestore
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! V9: wrpr %g6, %fp, %canrestore ! encoding: [0x97,0x91,0x80,0x1e]
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wrpr %g6,%i6,%canrestore
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%cleanwin
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! V9: wrpr %g6, %fp, %cleanwin ! encoding: [0x99,0x91,0x80,0x1e]
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wrpr %g6,%i6,%cleanwin
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%otherwin
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! V9: wrpr %g6, %fp, %otherwin ! encoding: [0x9b,0x91,0x80,0x1e]
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wrpr %g6,%i6,%otherwin
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,%i6,%wstate
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! V9: wrpr %g6, %fp, %wstate ! encoding: [0x9d,0x91,0x80,0x1e]
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wrpr %g6,%i6,%wstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tpc
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! V9: wrpr %g6, 255, %tpc ! encoding: [0x81,0x91,0xa0,0xff]
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wrpr %g6,255,%tpc
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tnpc
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! V9: wrpr %g6, 255, %tnpc ! encoding: [0x83,0x91,0xa0,0xff]
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wrpr %g6,255,%tnpc
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tstate
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! V9: wrpr %g6, 255, %tstate ! encoding: [0x85,0x91,0xa0,0xff]
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wrpr %g6,255,%tstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tt
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! V9: wrpr %g6, 255, %tt ! encoding: [0x87,0x91,0xa0,0xff]
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wrpr %g6,255,%tt
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tick
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! V9: wrpr %g6, 255, %tick ! encoding: [0x89,0x91,0xa0,0xff]
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wrpr %g6,255,%tick
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tba
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! V9: wrpr %g6, 255, %tba ! encoding: [0x8b,0x91,0xa0,0xff]
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wrpr %g6,255,%tba
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%pstate
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! V9: wrpr %g6, 255, %pstate ! encoding: [0x8d,0x91,0xa0,0xff]
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wrpr %g6,255,%pstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%tl
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! V9: wrpr %g6, 255, %tl ! encoding: [0x8f,0x91,0xa0,0xff]
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wrpr %g6,255,%tl
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%pil
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! V9: wrpr %g6, 255, %pil ! encoding: [0x91,0x91,0xa0,0xff]
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wrpr %g6,255,%pil
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%cwp
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! V9: wrpr %g6, 255, %cwp ! encoding: [0x93,0x91,0xa0,0xff]
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wrpr %g6,255,%cwp
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%cansave
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! V9: wrpr %g6, 255, %cansave ! encoding: [0x95,0x91,0xa0,0xff]
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wrpr %g6,255,%cansave
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%canrestore
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! V9: wrpr %g6, 255, %canrestore ! encoding: [0x97,0x91,0xa0,0xff]
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wrpr %g6,255,%canrestore
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%cleanwin
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! V9: wrpr %g6, 255, %cleanwin ! encoding: [0x99,0x91,0xa0,0xff]
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wrpr %g6,255,%cleanwin
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%otherwin
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! V9: wrpr %g6, 255, %otherwin ! encoding: [0x9b,0x91,0xa0,0xff]
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wrpr %g6,255,%otherwin
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: wrpr %g6,255,%wstate
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! V9: wrpr %g6, 255, %wstate ! encoding: [0x9d,0x91,0xa0,0xff]
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wrpr %g6,255,%wstate
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tpc,%i5
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! V9: rdpr %tpc, %i5 ! encoding: [0xbb,0x50,0x00,0x00]
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rdpr %tpc,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tnpc,%i5
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! V9: rdpr %tnpc, %i5 ! encoding: [0xbb,0x50,0x40,0x00]
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rdpr %tnpc,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tstate,%i5
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! V9: rdpr %tstate, %i5 ! encoding: [0xbb,0x50,0x80,0x00]
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rdpr %tstate,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tt,%i5
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! V9: rdpr %tt, %i5 ! encoding: [0xbb,0x50,0xc0,0x00]
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rdpr %tt,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tick,%i5
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! V9: rdpr %tick, %i5 ! encoding: [0xbb,0x51,0x00,0x00]
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rdpr %tick,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tba,%i5
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! V9: rdpr %tba, %i5 ! encoding: [0xbb,0x51,0x40,0x00]
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rdpr %tba,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %pstate,%i5
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! V9: rdpr %pstate, %i5 ! encoding: [0xbb,0x51,0x80,0x00]
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rdpr %pstate,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %tl,%i5
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! V9: rdpr %tl, %i5 ! encoding: [0xbb,0x51,0xc0,0x00]
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rdpr %tl,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %pil,%i5
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! V9: rdpr %pil, %i5 ! encoding: [0xbb,0x52,0x00,0x00]
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rdpr %pil,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %cwp,%i5
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! V9: rdpr %cwp, %i5 ! encoding: [0xbb,0x52,0x40,0x00]
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rdpr %cwp,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %cansave,%i5
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! V9: rdpr %cansave, %i5 ! encoding: [0xbb,0x52,0x80,0x00]
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rdpr %cansave,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
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! V8-NEXT: rdpr %canrestore,%i5
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! V9: rdpr %canrestore, %i5 ! encoding: [0xbb,0x52,0xc0,0x00]
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rdpr %canrestore,%i5
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! V8: error: instruction requires a CPU feature not currently enabled
|
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! V8-NEXT: rdpr %cleanwin,%i5
|
||||
! V9: rdpr %cleanwin, %i5 ! encoding: [0xbb,0x53,0x00,0x00]
|
||||
rdpr %cleanwin,%i5
|
||||
! V8: error: instruction requires a CPU feature not currently enabled
|
||||
! V8-NEXT: rdpr %otherwin,%i5
|
||||
! V9: rdpr %otherwin, %i5 ! encoding: [0xbb,0x53,0x40,0x00]
|
||||
rdpr %otherwin,%i5
|
||||
! V8: error: instruction requires a CPU feature not currently enabled
|
||||
! V8-NEXT: rdpr %wstate,%i5
|
||||
! V9: rdpr %wstate, %i5 ! encoding: [0xbb,0x53,0x80,0x00]
|
||||
rdpr %wstate,%i5
|
||||
|
||||
Loading…
Reference in New Issue
Block a user