[Hexagon] Add definitions for trap/pause instructions

Also add tests for other instructions from HexagonSystemInst.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267162 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Hexagon/HexagonSystemInst.td

@@ -111,3 +111,24 @@ def Y2_isync: JRInst <(outs), (ins),
     let Inst{9-0} = 0b0000000010;
   }
 
+//===----------------------------------------------------------------------===//
+//                     System/User instructions.
+//===----------------------------------------------------------------------===//
+// traps and pause
+let hasSideEffects = 0, isSolo = 1 in
+class J2_MISC_TRAP_PAUSE<string mnemonic, bits<2> MajOp>
+  : JRInst
+  <(outs), (ins u8Imm:$u8),
+   #mnemonic#"(#$u8)"> {
+    bits<8> u8;
+
+    let IClass = 0b0101;
+    let Inst{27-24} = 0b0100;
+    let Inst{23-22} = MajOp;
+    let Inst{12-8} = u8{7-3};
+    let Inst{4-2} = u8{2-0};
+  }
+def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>;
+def J2_trap1 : J2_MISC_TRAP_PAUSE<"trap1", 0b10>;
+def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>;
+

test/MC/Hexagon/instructions/system_user.s

@@ -24,3 +24,39 @@ dcfetch(r17 + #168)
 # Send value to ETM trace
 # CHECK: 00 c0 51 62
 trace(r17)
+
+# CHECK: 00 c0 00 a0
+dccleana(r0)
+
+# CHECK: 00 c0 41 a0
+dccleaninva(r1)
+
+# CHECK: 00 c0 22 a0
+dcinva(r2)
+
+# CHECK: 00 c0 c3 a0
+dczeroa(r3)
+
+# CHECK: 00 c0 c4 56
+icinva(r4)
+
+# CHECK: 02 c0 c0 57
+isync
+
+# CHECK: 00 c6 05 a6
+l2fetch(r5, r6)
+
+# CHECK: 00 c8 87 a6
+l2fetch(r7, r9:8)
+
+# CHECK: 1c df 40 54
+pause(#255)
+
+# CHECK: 00 c0 40 a8
+syncht
+
+# CHECK: 18 df 00 54
+trap0(#254)
+
+# CHECK: 14 df 80 54
+trap1(#253)