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[ARM] Fix for MVE load/store stack accesses
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372114 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Green
parent
1d7df59e12
commit
59654524ce
@ -1503,8 +1503,12 @@ static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF,
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/// instructions will require a scratch register during their expansion later.
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// FIXME: Move to TII?
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static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
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const TargetFrameLowering *TFI) {
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const TargetFrameLowering *TFI,
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bool &HasNonSPFrameIndex) {
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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unsigned Limit = (1 << 12) - 1;
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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@ -1519,6 +1523,11 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
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break;
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}
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const MCInstrDesc &MCID = MI.getDesc();
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const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
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if (RegClass && !RegClass->contains(ARM::SP))
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HasNonSPFrameIndex = true;
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// Otherwise check the addressing mode.
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switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
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case ARMII::AddrMode3:
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@ -1541,6 +1550,15 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
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// Addressing modes 4 & 6 (load/store) instructions can't encode an
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// immediate offset for stack references.
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return 0;
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case ARMII::AddrModeT2_i7:
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Limit = std::min(Limit, ((1U << 7) - 1) * 1);
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break;
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case ARMII::AddrModeT2_i7s2:
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Limit = std::min(Limit, ((1U << 7) - 1) * 2);
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break;
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case ARMII::AddrModeT2_i7s4:
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Limit = std::min(Limit, ((1U << 7) - 1) * 4);
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break;
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default:
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break;
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}
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@ -1784,6 +1802,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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EstimatedStackSize += 16; // For possible paddings.
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unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit;
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bool HasNonSPFrameIndex = false;
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if (AFI->isThumb1OnlyFunction()) {
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// For Thumb1, don't bother to iterate over the function. The only
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// instruction that requires an emergency spill slot is a store to a
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@ -1804,7 +1823,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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EstimatedRSStackSizeLimit = (1U << 8) * 4;
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EstimatedRSFixedSizeLimit = (1U << 5) * 4;
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} else {
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EstimatedRSStackSizeLimit = estimateRSStackSizeLimit(MF, this);
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EstimatedRSStackSizeLimit =
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estimateRSStackSizeLimit(MF, this, HasNonSPFrameIndex);
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EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit;
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}
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// Final estimate of whether sp or bp-relative accesses might require
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@ -1830,12 +1850,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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HasFP && (MaxFixedOffset - MaxFPOffset) > (int)EstimatedRSFixedSizeLimit;
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bool BigFrameOffsets = HasLargeStack || !HasBPOrFixedSP ||
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HasLargeArgumentList;
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HasLargeArgumentList || HasNonSPFrameIndex;
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LLVM_DEBUG(dbgs() << "EstimatedLimit: " << EstimatedRSStackSizeLimit
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<< "; EstimatedStack" << EstimatedStackSize
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<< "; EstimatedFPStack" << MaxFixedOffset - MaxFPOffset
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<< "; BigFrameOffsets: " << BigFrameOffsets
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<< "\n");
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<< "; EstimatedStack: " << EstimatedStackSize
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<< "; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset
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<< "; BigFrameOffsets: " << BigFrameOffsets << "\n");
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if (BigFrameOffsets ||
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!CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
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AFI->setHasStackFrame(true);
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185
test/CodeGen/Thumb2/mve-stacksplot.mir
Normal file
185
test/CodeGen/Thumb2/mve-stacksplot.mir
Normal file
@ -0,0 +1,185 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
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---
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name: func0
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -16, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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; CHECK-LABEL: name: func0
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
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; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)
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; CHECK: $r0 = tMOVr killed $sp, 14, $noreg
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; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg :: (load 4 from %stack.0 + 12)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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---
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name: func1
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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; CHECK-LABEL: name: func1
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
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; CHECK: $sp = frame-setup t2SUBri killed $sp, 1216, 14, $noreg, $noreg
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; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)
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; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg
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; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg :: (load 4 from %stack.0)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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