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ARM SRS and RFE instructions are not code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1721,11 +1721,10 @@ def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
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}
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}
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// Store Return State is a system instruction -- for disassembly only
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let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
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// Store Return State
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// FIXME: This should not use submode!
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def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
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NoItinerary, "srs${amode}\tsp!, $mode",
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[/* For disassembly only; pattern left blank */]> {
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NoItinerary, "srs${amode}\tsp!, $mode", []> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b110; // W = 1
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let Inst{19-8} = 0xd05;
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@ -1733,31 +1732,27 @@ def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
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}
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def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
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NoItinerary, "srs${amode}\tsp, $mode",
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[/* For disassembly only; pattern left blank */]> {
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NoItinerary, "srs${amode}\tsp, $mode", []> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b100; // W = 0
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let Inst{19-8} = 0xd05;
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let Inst{7-5} = 0b000;
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}
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// Return From Exception is a system instruction -- for disassembly only
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// Return From Exception
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def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
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NoItinerary, "rfe${amode}\t$base!",
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[/* For disassembly only; pattern left blank */]> {
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NoItinerary, "rfe${amode}\t$base!", []> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b011; // W = 1
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let Inst{15-0} = 0x0a00;
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}
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def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
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NoItinerary, "rfe${amode}\t$base",
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[/* For disassembly only; pattern left blank */]> {
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NoItinerary, "rfe${amode}\t$base", []> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b001; // W = 0
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let Inst{15-0} = 0x0a00;
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}
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} // isCodeGenOnly = 1
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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