RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-21 03:00:45 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[PeepholeOpt] Don't stop simplifying copies on sequence of subregs

Browse Source 
This patch removes an overly conservative check that would prevent
simplifying copies when the value we were tracking would go through
several subregister indices.
Indeed, the intend of this check was to not track values whenever
we have to compose subregister, but actually what the check was
doing was bailing anytime we see a second subreg, even if that
second subreg would actually be the new source of truth (as opposed
to a part of that subreg).

Differential Revision: https://reviews.llvm.org/D59891

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2019-03-27 17:27:56 +00:00
parent d0d95f2d77
commit 5a4d441633
2 changed files with 35 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -1900,13 +1900,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
// Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
// Check if one of the operand defines the subreg we are interested in.
for (const RegSubRegPairAndIdx &RegSeqInput : RegSeqInputRegs) {
if (RegSeqInput.SubIdx == DefSubReg) {
if (RegSeqInput.SubReg)
// Bail if we have to compose sub registers.
return ValueTrackerResult();
if (RegSeqInput.SubIdx == DefSubReg)
return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
}
}
// If the subreg we are tracking is super-defined by another subreg,

34
test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir Normal file
View File

@ -0,0 +1,34 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# Check that when we jump through several subregisters in sequence of
# reg_sequence we can still find a plain src for a copy.
# In this specific test, we want %4 to read directly from %1 and
# %5 from %0. These values come from the respective chains:
# %4 -> %3.sub0 -> %2.sub1 -> %1
# %5 -> %3.sub1 -> %2.sub0 -> %0
#
# We used to not simplify this because we were bailing when two
# subreg indices were in the same chain (%3.subX and %2.subY)
---
name: reg_sequence_removal
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: reg_sequence_removal
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[REG_SEQUENCE]].sub1, %subreg.sub0, [[REG_SEQUENCE]].sub0, %subreg.sub1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN: KILL [[COPY3]], implicit [[COPY2]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%3:vreg_64 = REG_SEQUENCE %2.sub1, %subreg.sub0, %2.sub0, %subreg.sub1
%4:vgpr_32 = COPY %3.sub0
%5:vgpr_32 = COPY %3.sub1
KILL implicit %4, %5
...