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Add XCore intrinsics for getps, setps, setsr and clrsr.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-03-15 13:45:47 +00:00
parent 625eec10fe
commit 5aad8b3e78
4 changed files with 66 additions and 3 deletions
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5
include/llvm/IntrinsicsXCore.td
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@ -9,8 +9,13 @@
//===----------------------------------------------------------------------===//
let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
// Miscellaneous instructions.
def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;
def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;
def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;
// Resource instructions.
def int_xcore_getr : Intrinsic<[llvm_anyptr_ty],[llvm_i32_ty]>;

28
lib/Target/XCore/XCoreInstrInfo.td
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@ -308,6 +308,16 @@ multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
!strconcat(OpcStr, " $b"),
[(OpNode immU16:$b)]>;
}
multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
def _u6: _FU6<
(outs), (ins i32imm:$b),
!strconcat(OpcStr, " $b"),
[(Int immU6:$b)]>;
def _lu6: _FLU6<
(outs), (ins i32imm:$b),
!strconcat(OpcStr, " $b"),
[(Int immU16:$b)]>;
}
multiclass FU6_LU6_np<string OpcStr> {
def _u6: _FU6<
@ -638,8 +648,8 @@ defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
}
}
// TODO extdp, kentsp, krestsp, blat, setsr
// clrsr, getsr, kalli
// TODO extdp, kentsp, krestsp, blat
// getsr, kalli
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def BRBU_u6 : _FU6<
(outs),
@ -678,6 +688,10 @@ def LDAWCP_lu6: _FLRU6<
"ldaw r11, cp[$a]",
[(set R11, ADDRcpii:$a)]>;
defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
// U10
// TODO ldwcpl, blacp
@ -818,7 +832,7 @@ def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
// Two operand long
// TODO setclk, setrdy, setpsc, endin, peek,
// getd, testlcl, tinitlr, getps, setps
// getd, testlcl, tinitlr
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"bitrev $dst, $src",
[(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
@ -839,6 +853,14 @@ def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
"settw res[$r], $val",
[(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"get $dst, ps[$src]",
[(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
"set ps[$src1], $src2",
[(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
// One operand short
// TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, clrtp
// setdp, setcp, setev, kcall

18
test/CodeGen/XCore/ps-intrinsics.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc < %s -march=xcore | FileCheck %s
declare i32 @llvm.xcore.getps(i32)
declare void @llvm.xcore.setps(i32, i32)
define i32 @getps(i32 %reg) nounwind {
; CHECK: getps:
; CHECK: get r0, ps[r0]
%result = call i32 @llvm.xcore.getps(i32 %reg)
ret i32 %result
}
define void @setps(i32 %reg, i32 %value) nounwind {
; CHECK: setps:
; CHECK: set ps[r0], r1
call void @llvm.xcore.setps(i32 %reg, i32 %value)
ret void
}

18
test/CodeGen/XCore/sr-intrinsics.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc < %s -march=xcore | FileCheck %s
declare void @llvm.xcore.setsr(i32)
declare void @llvm.xcore.clrsr(i32)
define void @setsr() nounwind {
; CHECK: setsr:
; CHECK: setsr 128
call void @llvm.xcore.setsr(i32 128)
ret void
}
define void @clrsr() nounwind {
; CHECK: clrsr:
; CHECK: clrsr 128
call void @llvm.xcore.clrsr(i32 128)
ret void
}