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Non-fast-isel followup to 129634; correctly handle branches controlled
by non-CMP expressions. The executable test case (129821) would test this as well, if we had an "-O0 -disable-arm-fast-isel" LLVM-GCC tester. Alas, the ARM assembly would be very difficult to check with FileCheck. The thumb2-cbnz.ll test is affected; it generates larger code (tst.w vs. cmp #0), but I believe the new version is correct. rdar://problem/9298790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131261 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3535,9 +3535,16 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Node->getOperand(2));
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} else {
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// We test only the i1 bit. Skip the AND if UNDEF.
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Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF ||
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(Tmp2.getOpcode() == ISD::AND &&
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Tmp2.getConstantOperandVal(1) == 1)) ?
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Tmp2 :
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DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
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DAG.getConstant(1, Tmp2.getValueType()));
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getConstant(0, Tmp2.getValueType()),
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DAG.getCondCode(ISD::SETNE), Tmp3,
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DAG.getConstant(0, Tmp3.getValueType()),
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Node->getOperand(2));
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}
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Results.push_back(Tmp1);
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@ -20,9 +20,10 @@ bb7: ; preds = %bb3
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br i1 %a, label %bb11, label %bb9
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bb9: ; preds = %bb7
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; CHECK: cmp r0, #0
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; CHECK: cmp r0, #0
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; CHECK-NEXT: cbnz
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; CHECK: tst.w r0, #1
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; CHECK: tst.w r0, #1
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; CHECK: tst.w r0, #1
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; CHECK: bne
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%0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0]
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br label %bb11
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