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Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's

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return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel 2008-03-10 15:42:14 +00:00
parent 0404cd97e4
commit 5b8f82e35b
18 changed files with 113 additions and 66 deletions
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13
include/llvm/Target/TargetLowering.h
View File

@ -109,9 +109,8 @@ public:
/// srl/add/sra. /// srl/add/sra.
bool isPow2DivCheap() const { return Pow2DivIsCheap; } bool isPow2DivCheap() const { return Pow2DivIsCheap; }
/// getSetCCResultTy - Return the ValueType of the result of setcc operations. /// getSetCCResultType - Return the ValueType of the result of setcc operations.
/// virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
/// getSetCCResultContents - For targets without boolean registers, this flag /// getSetCCResultContents - For targets without boolean registers, this flag
/// returns information about the contents of the high-bits in the setcc /// returns information about the contents of the high-bits in the setcc
@ -707,10 +706,6 @@ protected:
/// amounts. This type defaults to the pointer type. /// amounts. This type defaults to the pointer type.
void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
/// setSetCCResultType - Describe the type that shoudl be used as the result
/// of a setcc operation. This defaults to the pointer type.
void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
/// setSetCCResultContents - Specify how the target extends the result of a /// setSetCCResultContents - Specify how the target extends the result of a
/// setcc operation in a register. /// setcc operation in a register.
void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
@ -1259,10 +1254,6 @@ private:
/// it. /// it.
bool Pow2DivIsCheap; bool Pow2DivIsCheap;
/// SetCCResultTy - The type that SetCC operations use. This defaults to the
/// PointerTy.
MVT::ValueType SetCCResultTy;
/// SetCCResultContents - Information about the contents of the high-bits in /// SetCCResultContents - Information about the contents of the high-bits in
/// the result of a setcc comparison operation. /// the result of a setcc comparison operation.
SetCCResultValue SetCCResultContents; SetCCResultValue SetCCResultContents;

10
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2605,7 +2605,7 @@ SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
return N2; return N2;
// Determine if the condition we're dealing with is constant // Determine if the condition we're dealing with is constant
SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
if (SCC.Val) AddToWorkList(SCC.Val); if (SCC.Val) AddToWorkList(SCC.Val);
if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
@ -5077,7 +5077,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
// Determine if the condition we're dealing with is constant // Determine if the condition we're dealing with is constant
SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
if (SCC.Val) AddToWorkList(SCC.Val); if (SCC.Val) AddToWorkList(SCC.Val);
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
@ -5157,7 +5157,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
SDOperand Temp, SCC; SDOperand Temp, SCC;
// cast from setcc result type to select result type // cast from setcc result type to select result type
if (AfterLegalize) { if (AfterLegalize) {
SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
if (N2.getValueType() < SCC.getValueType()) if (N2.getValueType() < SCC.getValueType())
Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
else else
@ -5182,8 +5182,8 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// otherwise, go ahead with the folds. // otherwise, go ahead with the folds.
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
MVT::ValueType XType = N0.getValueType(); MVT::ValueType XType = N0.getValueType();
if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
if (Res.getValueType() != VT) if (Res.getValueType() != VT)
Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
return Res; return Res;

57
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -3186,7 +3186,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType IVT = MVT::ValueType IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
SignBit, DAG.getConstant(0, IVT), ISD::SETLT); SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
// Get the absolute value of the result. // Get the absolute value of the result.
SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
@ -3522,7 +3522,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break; break;
case ISD::CTTZ: case ISD::CTTZ:
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
DAG.getConstant(MVT::getSizeInBits(NVT), NVT), DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ); ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@ -3574,7 +3574,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
MVT::ValueType VT = Node->getValueType(0); MVT::ValueType VT = Node->getValueType(0);
Tmp2 = DAG.getConstantFP(0.0, VT); Tmp2 = DAG.getConstantFP(0.0, VT);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
ISD::SETUGT);
Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
break; break;
@ -3780,7 +3781,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp2 = DAG.getConstantFP(apf, VT); Tmp2 = DAG.getConstantFP(apf, VT);
Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
Node->getOperand(0), Tmp2, ISD::SETLT); Node->getOperand(0), Tmp2, ISD::SETLT);
True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
False = DAG.getNode(ISD::FP_TO_SINT, NVT, False = DAG.getNode(ISD::FP_TO_SINT, NVT,
@ -4124,9 +4125,12 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
break; break;
case ISD::SETCC: case ISD::SETCC:
assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), && "SetCC type is not legal??");
Node->getOperand(1), Node->getOperand(2)); Result = DAG.getNode(ISD::SETCC,
TLI.getSetCCResultType(Node->getOperand(0)),
Node->getOperand(0), Node->getOperand(1),
Node->getOperand(2));
break; break;
case ISD::TRUNCATE: case ISD::TRUNCATE:
@ -4484,7 +4488,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
break; break;
case ISD::CTTZ: case ISD::CTTZ:
// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
DAG.getConstant(MVT::getSizeInBits(NVT), NVT), DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ); ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@ -4748,11 +4752,12 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
Tmp2 = DAG.getConstant(0, MVT::i32); Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) { if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
CC);
LHS = ExpandLibCall(TLI.getLibcallName(LC2), LHS = ExpandLibCall(TLI.getLibcallName(LC2),
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy); false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDOperand(); Tmp2 = SDOperand();
@ -4773,11 +4778,11 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
// BNE crN, L: // BNE crN, L:
// FCMP crN, lo1, lo2 // FCMP crN, lo1, lo2
// The following can be improved, but not that much. // The following can be improved, but not that much.
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
Tmp2 = SDOperand(); Tmp2 = SDOperand();
@ -4835,14 +4840,15 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
// NOTE: on targets without efficient SELECT of bools, we can always use // NOTE: on targets without efficient SELECT of bools, we can always use
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
false, DagCombineInfo); LowCC, false, DagCombineInfo);
if (!Tmp1.Val) if (!Tmp1.Val)
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
CCCode, false, DagCombineInfo); CCCode, false, DagCombineInfo);
if (!Tmp2.Val) if (!Tmp2.Val)
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
RHSHi,CC);
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
@ -4859,10 +4865,11 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
Tmp1 = Tmp2; Tmp1 = Tmp2;
Tmp2 = SDOperand(); Tmp2 = SDOperand();
} else { } else {
Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
ISD::SETEQ, false, DagCombineInfo); ISD::SETEQ, false, DagCombineInfo);
if (!Result.Val) if (!Result.Val)
Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
ISD::SETEQ);
Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
Result, Tmp1, Tmp2)); Result, Tmp1, Tmp2));
Tmp1 = Result; Tmp1 = Result;
@ -5336,7 +5343,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
SDOperand SignedConv = ExpandIntToFP(true, DestTy, SDOperand SignedConv = ExpandIntToFP(true, DestTy,
DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi)); DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, Hi.getValueType()), DAG.getConstant(0, Hi.getValueType()),
ISD::SETLT); ISD::SETLT);
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@ -5489,7 +5496,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
DAG.getConstant(0, Op0.getValueType()), DAG.getConstant(0, Op0.getValueType()),
ISD::SETLT); ISD::SETLT);
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@ -5895,7 +5902,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
ExpandOp(Node->getOperand(0), Lo, Hi); ExpandOp(Node->getOperand(0), Lo, Hi);
SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
ISD::SETNE); ISD::SETNE);
SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
@ -5910,7 +5917,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
ExpandOp(Node->getOperand(0), Lo, Hi); ExpandOp(Node->getOperand(0), Lo, Hi);
SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
ISD::SETNE); ISD::SETNE);
SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);

27
lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
View File

@ -632,7 +632,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
GetExpandedOp(N->getOperand(0), Lo, Hi); GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType(); MVT::ValueType NVT = Lo.getValueType();
SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, NVT), ISD::SETNE); DAG.getConstant(0, NVT), ISD::SETNE);
SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
@ -660,7 +660,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
GetExpandedOp(N->getOperand(0), Lo, Hi); GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType(); MVT::ValueType NVT = Lo.getValueType();
SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Lo, SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
DAG.getConstant(0, NVT), ISD::SETNE); DAG.getConstant(0, NVT), ISD::SETNE);
SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
@ -1031,7 +1031,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
SDOperand Lo, Hi; SDOperand Lo, Hi;
GetExpandedOp(Source, Lo, Hi); GetExpandedOp(Source, Lo, Hi);
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, Hi.getValueType()), DAG.getConstant(0, Hi.getValueType()),
ISD::SETLT); ISD::SETLT);
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@ -1113,11 +1113,11 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
// FCMP crN, lo1, lo2 // FCMP crN, lo1, lo2
// The following can be improved, but not that much. // The following can be improved, but not that much.
SDOperand Tmp1, Tmp2, Tmp3; SDOperand Tmp1, Tmp2, Tmp3;
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
NewRHS = SDOperand(); // LHS is the result, not a compare. NewRHS = SDOperand(); // LHS is the result, not a compare.
@ -1174,14 +1174,14 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
SDOperand Tmp1, Tmp2; SDOperand Tmp1, Tmp2;
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
false, DagCombineInfo); false, DagCombineInfo);
if (!Tmp1.Val) if (!Tmp1.Val)
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
CCCode, false, DagCombineInfo); CCCode, false, DagCombineInfo);
if (!Tmp2.Val) if (!Tmp2.Val)
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
DAG.getCondCode(CCCode)); DAG.getCondCode(CCCode));
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
@ -1201,10 +1201,11 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
return; return;
} }
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
ISD::SETEQ, false, DagCombineInfo); ISD::SETEQ, false, DagCombineInfo);
if (!NewLHS.Val) if (!NewLHS.Val)
NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
ISD::SETEQ);
NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
NewLHS, Tmp1, Tmp2); NewLHS, Tmp1, Tmp2);
NewRHS = SDOperand(); NewRHS = SDOperand();

7
lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
View File

@ -186,9 +186,10 @@ SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
} }
SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0), && "SetCC type is not legal??");
N->getOperand(1), N->getOperand(2)); return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
N->getOperand(0), N->getOperand(1), N->getOperand(2));
} }
SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {

6
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1440,7 +1440,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
// Emit the range check for the jump table, and branch to the default // Emit the range check for the jump table, and branch to the default
// block for the switch statement if the value being switched on exceeds // block for the switch statement if the value being switched on exceeds
// the largest case in the switch. // the largest case in the switch.
SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
DAG.getConstant(JTH.Last-JTH.First,VT), DAG.getConstant(JTH.Last-JTH.First,VT),
ISD::SETUGT); ISD::SETUGT);
@ -1473,7 +1473,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B)
DAG.getConstant(B.First, VT)); DAG.getConstant(B.First, VT));
// Check range // Check range
SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
DAG.getConstant(B.Range, VT), DAG.getConstant(B.Range, VT),
ISD::SETUGT); ISD::SETUGT);
@ -1526,7 +1526,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
SwitchVal, SwitchVal,
DAG.getConstant(B.Mask, DAG.getConstant(B.Mask,
TLI.getPointerTy())); TLI.getPointerTy()));
SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
DAG.getConstant(0, TLI.getPointerTy()), DAG.getConstant(0, TLI.getPointerTy()),
ISD::SETNE); ISD::SETNE);
SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),

9
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -191,7 +191,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
IsLittleEndian = TD->isLittleEndian(); IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false; UsesGlobalOffsetTable = false;
ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
ShiftAmtHandling = Undefined; ShiftAmtHandling = Undefined;
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
@ -372,6 +372,13 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return NULL; return NULL;
} }
MVT::ValueType
TargetLowering::getSetCCResultType(const SDOperand &) const {
return getValueType(TD->getIntPtrType());
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of /// getVectorTypeBreakdown - Vector types are broken down into some number of
/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.

6
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -40,7 +40,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
// Set up the TargetLowering object. // Set up the TargetLowering object.
//I am having problems with shr n ubyte 1 //I am having problems with shr n ubyte 1
setShiftAmountType(MVT::i64); setShiftAmountType(MVT::i64);
setSetCCResultType(MVT::i64);
setSetCCResultContents(ZeroOrOneSetCCResult); setSetCCResultContents(ZeroOrOneSetCCResult);
setUsesGlobalOffsetTable(true); setUsesGlobalOffsetTable(true);
@ -151,6 +150,11 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
computeRegisterProperties(); computeRegisterProperties();
} }
MVT::ValueType
AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i64;
}
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) { switch (Opcode) {
default: return 0; default: return 0;

3
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -66,6 +66,9 @@ namespace llvm {
public: public:
explicit AlphaTargetLowering(TargetMachine &TM); explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);

3
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -103,6 +103,9 @@ namespace llvm {
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);

5
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -57,7 +57,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// br.ret insn // br.ret insn
setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::RET, MVT::Other, Custom);
setSetCCResultType(MVT::i1);
setShiftAmountType(MVT::i64); setShiftAmountType(MVT::i64);
setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f32 , Expand);
@ -137,6 +136,10 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
} }
} }
MVT::ValueType
IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i1;
}
std::vector<SDOperand> std::vector<SDOperand>
IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {

1
lib/Target/IA64/IA64ISelLowering.h
View File

@ -47,6 +47,7 @@ namespace llvm {
unsigned VirtGPR; // this is public so it can be accessed in the selector unsigned VirtGPR; // this is public so it can be accessed in the selector
// for ISD::RET. add an accessor instead? FIXME // for ISD::RET. add an accessor instead? FIXME
const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const;
MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// LowerArguments - This hook must be implemented to indicate how we should /// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG. /// lower the arguments for the specified function, into the specified DAG.

7
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -52,7 +52,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
{ {
// Mips does not have i1 type, so use i32 for // Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...). // setcc operations results (slt, sgt, ...).
setSetCCResultType(MVT::i32);
setSetCCResultContents(ZeroOrOneSetCCResult); setSetCCResultContents(ZeroOrOneSetCCResult);
// JumpTable targets must use GOT when using PIC_ // JumpTable targets must use GOT when using PIC_
@ -112,6 +111,12 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
} }
MVT::ValueType
MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i32;
}
SDOperand MipsTargetLowering:: SDOperand MipsTargetLowering::
LowerOperation(SDOperand Op, SelectionDAG &DAG) LowerOperation(SDOperand Op, SelectionDAG &DAG)
{ {

3
lib/Target/Mips/MipsISelLowering.h
View File

@ -62,6 +62,9 @@ namespace llvm {
// DAG node. // DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
MVT::ValueType getSetCCResultType(const SDOperand &) const;
private: private:
// Lower Operand helpers // Lower Operand helpers
SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);

8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -324,7 +324,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
} }
setSetCCResultType(MVT::i32);
setShiftAmountType(MVT::i32); setShiftAmountType(MVT::i32);
setSetCCResultContents(ZeroOrOneSetCCResult); setSetCCResultContents(ZeroOrOneSetCCResult);
@ -407,6 +406,13 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
} }
} }
MVT::ValueType
PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i32;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Node matching predicates, for use by the tblgen matching code. // Node matching predicates, for use by the tblgen matching code.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

3
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -213,6 +213,9 @@ namespace llvm {
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and /// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address /// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address. /// can be legally represented as pre-indexed load / store address.

8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -57,7 +57,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// X86 is weird, it always uses i8 for shift amounts and setcc results. // X86 is weird, it always uses i8 for shift amounts and setcc results.
setShiftAmountType(MVT::i8); setShiftAmountType(MVT::i8);
setSetCCResultType(MVT::i8);
setSetCCResultContents(ZeroOrOneSetCCResult); setSetCCResultContents(ZeroOrOneSetCCResult);
setSchedulingPreference(SchedulingForRegPressure); setSchedulingPreference(SchedulingForRegPressure);
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
@ -728,6 +727,13 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setPrefLoopAlignment(16); setPrefLoopAlignment(16);
} }
MVT::ValueType
X86TargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i8;
}
/// getMaxByValAlign - Helper for getByValTypeAlignment to determine /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
/// the desired ByVal argument alignment. /// the desired ByVal argument alignment.
static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {

3
lib/Target/X86/X86ISelLowering.h
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@ -375,6 +375,9 @@ namespace llvm {
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified /// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.