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[fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle
instructions that define aggregate types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146492 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -941,106 +941,6 @@ FastISel::SelectExtractValue(const User *U) {
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return true;
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}
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bool
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FastISel::SelectInsertValue(const User *U) {
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return false;
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const InsertValueInst *IVI = dyn_cast<InsertValueInst>(U);
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if (!IVI)
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return false;
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// Only try to handle inserts of legal types. But also allow i16/i8/i1 because
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// they're easy.
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const Value *Val = IVI->getOperand(1);
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Type *ValTy = Val->getType();
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EVT ValVT = TLI.getValueType(ValTy, /*AllowUnknown=*/true);
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if (!ValVT.isSimple())
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return false;
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MVT VT = ValVT.getSimpleVT();
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if (!TLI.isTypeLegal(VT) && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
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return false;
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// Get the Val register.
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unsigned ValReg = getRegForValue(Val);
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if (ValReg == 0) return false;
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const Value *Agg = IVI->getOperand(0);
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Type *AggTy = Agg->getType();
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// TODO: Is there a better way to do this? For each insertvalue we allocate
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// a new set of virtual registers, which results in a large number of
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// loads/stores from/to the stack that copies the aggregate all over the place
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// and results in lots of spill code. I believe this is necessary to preserve
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// SSA form, but maybe there's something we could do to improve this.
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// Get the Aggregate base register.
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unsigned AggBaseReg;
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DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Agg);
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if (I != FuncInfo.ValueMap.end())
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AggBaseReg = I->second;
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else if (isa<Instruction>(Agg))
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AggBaseReg = FuncInfo.InitializeRegForValue(Agg);
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else if (isa<UndefValue>(Agg))
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// In this case we don't need to allocate a new set of register that will
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// never be defined. Just copy Val into the proper result registers.
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AggBaseReg = 0;
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else
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return false; // fast-isel can't handle aggregate constants at the moment
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// Create result register(s).
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unsigned ResultBaseReg = FuncInfo.CreateRegs(AggTy);
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// Get the actual result register, which is an offset from the base register.
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unsigned LinearIndex = ComputeLinearIndex(Agg->getType(), IVI->getIndices());
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SmallVector<EVT, 4> AggValueVTs;
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ComputeValueVTs(TLI, AggTy, AggValueVTs);
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// Copy the beginning value(s) from the original aggregate.
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unsigned SrcReg;
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unsigned DestReg;
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unsigned BaseRegOff = 0;
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unsigned i = 0;
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for (; i != LinearIndex; ++i) {
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unsigned NRE = TLI.getNumRegisters(FuncInfo.Fn->getContext(),
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AggValueVTs[i]);
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for (unsigned NRI = 0; NRI != NRE; NRI++) {
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if (AggBaseReg) {
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SrcReg = AggBaseReg + BaseRegOff + NRI;
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DestReg = ResultBaseReg + BaseRegOff + NRI;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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DestReg).addReg(SrcReg);
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}
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}
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BaseRegOff += NRE;
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}
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// FIXME: Handle aggregate inserts. Haven't seen these in practice, but..
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// Copy value(s) from the inserted value(s).
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DestReg = ResultBaseReg + BaseRegOff;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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DestReg).addReg(ValReg);
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++BaseRegOff;
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++i;
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// Copy remaining value(s) from the original aggregate.
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if (AggBaseReg) {
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for (unsigned NumAggValues = AggValueVTs.size(); i != NumAggValues; ++i) {
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unsigned NRE = TLI.getNumRegisters(FuncInfo.Fn->getContext(),
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AggValueVTs[i]);
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for (unsigned NRI = 0; NRI != NRE; NRI++) {
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SrcReg = AggBaseReg + BaseRegOff + NRI;
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DestReg = ResultBaseReg + BaseRegOff + NRI;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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DestReg).addReg(SrcReg);
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}
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BaseRegOff += NRE;
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}
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}
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UpdateValueMap(IVI, ResultBaseReg);
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return true;
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}
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bool
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FastISel::SelectOperator(const User *I, unsigned Opcode) {
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switch (Opcode) {
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@ -1148,9 +1048,6 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
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case Instruction::ExtractValue:
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return SelectExtractValue(I);
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case Instruction::InsertValue:
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return SelectInsertValue(I);
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case Instruction::PHI:
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llvm_unreachable("FastISel shouldn't visit PHI nodes!");
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