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Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is

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the same as ARM except that the condition code field is always set to ARMCC::AL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-29 00:26:13 +00:00
parent e4e7d56396
commit 5cdede43e9
1 changed files with 1 additions and 1 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -1600,7 +1600,7 @@ void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
unsigned Binary = getBinaryCodeForInstr(MI);
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
unsigned RegT = MI.getOperand(0).getReg();
RegT = ARMRegisterInfo::getRegisterNumbering(RegT);