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Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)

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Place the immediate to OR into a register so that it works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2011-10-06 21:51:21 +00:00
parent 7abb795635
commit 5e2cbc1133
1 changed files with 12 additions and 7 deletions
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19
lib/Target/ARM/ARMISelLowering.cpp
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@ -5613,7 +5613,8 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
// Incoming value: jbuf // Incoming value: jbuf
// ldr.n r1, LCPI1_4 // ldr.n r1, LCPI1_4
// add r1, pc // add r1, pc
// orr r1, r1, #1 // mov r2, #1
// orrs r1, r2
// add r2, $jbuf, #+4 ; &jbuf[1] // add r2, $jbuf, #+4 ; &jbuf[1]
// str r1, [r2] // str r1, [r2]
unsigned NewVReg1 = MRI->createVirtualRegister(TRC); unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
@ -5626,17 +5627,21 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
.addImm(PCLabelId); .addImm(PCLabelId);
// Set the low bit because of thumb mode. // Set the low bit because of thumb mode.
unsigned NewVReg3 = MRI->createVirtualRegister(TRC); unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
AddDefaultCC( AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg3) .addReg(ARM::CPSR, RegState::Define)
.addReg(NewVReg2, RegState::Kill) .addImm(1));
.addImm(0x01)));
unsigned NewVReg4 = MRI->createVirtualRegister(TRC); unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg4) AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
.addReg(ARM::CPSR, RegState::Define)
.addReg(NewVReg2, RegState::Kill)
.addReg(NewVReg3, RegState::Kill));
unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(36)); // &jbuf[1] :: pc .addImm(36)); // &jbuf[1] :: pc
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
.addReg(NewVReg3, RegState::Kill)
.addReg(NewVReg4, RegState::Kill) .addReg(NewVReg4, RegState::Kill)
.addReg(NewVReg5, RegState::Kill)
.addImm(0) .addImm(0)
.addMemOperand(FIMMO)); .addMemOperand(FIMMO));
} else { } else {