Add TargetInstrInfo::isMoveInstr() to support coalescing in register

allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2003-12-28 17:35:08 +00:00
parent aed386e6b0
commit 5e30002af7
3 changed files with 33 additions and 0 deletions

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@ -214,6 +214,16 @@ public:
return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
//
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
return false;
}
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.

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@ -51,3 +51,18 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
return false;
}
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid register-register move instruction");
sourceReg = MI.getOperand(1).getAllocatedRegNum();
destReg = MI.getOperand(0).getAllocatedRegNum();
return true;
}
return false;
}

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@ -169,6 +169,14 @@ public:
///
MachineInstr* createNOPinstr() const;
//
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const;
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.