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Add TargetInstrInfo::isMoveInstr() to support coalescing in register
allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10633 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -214,6 +214,16 @@ public:
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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return false;
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}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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@ -51,3 +51,18 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
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return false;
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}
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32) {
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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sourceReg = MI.getOperand(1).getAllocatedRegNum();
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destReg = MI.getOperand(0).getAllocatedRegNum();
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return true;
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}
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return false;
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}
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@ -169,6 +169,14 @@ public:
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///
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MachineInstr* createNOPinstr() const;
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const;
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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