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Revert r118457 and r118458. These won't hold for GPRs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-09 00:30:18 +00:00
parent 3afb024907
commit 5e559a22c1
2 changed files with 8 additions and 6 deletions
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1
lib/Target/ARM/ARMInstrInfo.td
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@ -278,7 +278,6 @@ def brtarget : Operand<OtherVT>;
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
int NumOperands = 2;
string EncoderMethod = "getRegisterListOpValue";
let PrintMethod = "printRegisterList";
}

13
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -378,11 +378,14 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &) const {
// {12-8} = Rd
// {7-0} = count
unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
SmallVectorImpl<MCFixup> &Fixups) const {
// Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
// register in the list, set the corresponding bit.
unsigned Binary = 0;
for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
Binary |= 1 << regno;
}
return Binary;
}