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https://github.com/RPCS3/llvm.git
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Compare dependence analysis with llvm instructions versus machine instrutions. the problem with using machine instructions and alias analysis is that aa does not handle tmp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20931 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner
parent
5ec3a63f6d
commit
5e9f352346
@ -141,7 +141,10 @@ void MSchedGraph::deleteNode(MSchedGraphNode *node) {
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//Create a graph for a machine block. The ignoreInstrs map is so that we ignore instructions
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//associated to the index variable since this is a special case in Modulo Scheduling.
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//We only want to deal with the body of the loop.
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MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ, AliasAnalysis &AA, TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs)
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MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ, AliasAnalysis &AA,
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TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm
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)
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: BB(bb), Target(targ) {
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//Make sure BB is not null,
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@ -150,7 +153,7 @@ MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
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//DEBUG(std::cerr << "Constructing graph for " << bb << "\n");
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//Create nodes and edges for this BB
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buildNodesAndEdges(AA, TD, ignoreInstrs);
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buildNodesAndEdges(AA, TD, ignoreInstrs, DA, machineTollvm);
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//Experimental!
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//addBranchEdges();
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@ -270,7 +273,10 @@ void MSchedGraph::addBranchEdges() {
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//Add edges between the nodes
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void MSchedGraph::buildNodesAndEdges(AliasAnalysis &AA, TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs) {
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void MSchedGraph::buildNodesAndEdges(AliasAnalysis &AA, TargetData &TD,
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std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA,
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std::map<MachineInstr*, Instruction*> &machineTollvm) {
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//Get Machine target information for calculating latency
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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@ -405,7 +411,7 @@ void MSchedGraph::buildNodesAndEdges(AliasAnalysis &AA, TargetData &TD, std::map
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}
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addMemEdges(memInstructions, AA, TD);
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addMemEdges(memInstructions, AA, TD, DA, machineTollvm);
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addMachRegEdges(regNumtoNodeMap);
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//Finally deal with PHI Nodes and Value*
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@ -584,7 +590,9 @@ void MSchedGraph::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >&
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//Add edges between all loads and stores
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//Can be less strict with alias analysis and data dependence analysis.
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void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, AliasAnalysis &AA, TargetData &TD) {
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void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, AliasAnalysis &AA,
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TargetData &TD, DependenceAnalyzer &DA,
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std::map<MachineInstr*, Instruction*> &machineTollvm) {
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//Get Target machine instruction info
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const TargetInstrInfo *TMI = Target.getInstrInfo();
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@ -598,11 +606,16 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, Alia
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//Get the machine opCode to determine type of memory instruction
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MachineOpCode srcNodeOpCode = srcInst->getOpcode();
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//All instructions after this one in execution order have an iteration delay of 0
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for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) {
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MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
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bool malias = false;
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DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
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DEBUG(std::cerr << "Inst1: " << *machineTollvm[srcInst] << "\n");
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DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
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DEBUG(std::cerr << "Inst2: " << *machineTollvm[destInst] << "\n");
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//Add Anti dependencies (store after load)
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//Source is a Load
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@ -613,14 +626,24 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, Alia
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//Get the Value* that we are reading from the load, always the first op
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const MachineOperand &mOp = srcInst->getOperand(0);
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assert((mOp.isUse() && (mOp.getType() == MachineOperand::MO_VirtualRegister)) && "Assumed first operand was a use and a value*\n");
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//Get the value* for the store
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const MachineOperand &mOp2 = destInst->getOperand(0);
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assert(mOp2.getType() == MachineOperand::MO_VirtualRegister && "Assumed first operand was a value*\n");
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if(mOp.hasAllocatedReg())
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if(mOp.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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if(mOp2.hasAllocatedReg())
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if(mOp2.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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//compare to DA
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DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], machineTollvm[destInst]);
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//Only add the edge if we can't verify that they do not alias
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if(AA.alias(mOp2.getVRegValue(),
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if(malias || AA.alias(mOp2.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
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mOp.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
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@ -630,23 +653,38 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, Alia
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep);
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assert(dr.dependences.size() == 1 && "Expected at least one dependence\n");
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}
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else
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assert(dr.dependences.size() == 0 && "Expected no dependence\n");
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}
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}
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//If source is a store, add output and true dependencies
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if(TMI->isStore(srcNodeOpCode)) {
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//Get the Value* that we are reading from the store (src), always the first op
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const MachineOperand &mOp = srcInst->getOperand(0);
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assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Assumed first operand was a use and a value*\n");
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//Get the Value* that we are reading from the load, always the first op
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const MachineOperand &mOp2 = srcInst->getOperand(0);
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assert((mOp2.isUse() && (mOp2.getType() == MachineOperand::MO_VirtualRegister)) && "Assumed first operand was a use and a value*\n");
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const MachineOperand &mOp = srcInst->getOperand(0);
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const MachineOperand &mOp2 = destInst->getOperand(0);
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if(mOp.hasAllocatedReg())
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if(mOp.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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if(mOp2.hasAllocatedReg())
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if(mOp2.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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//compare to DA
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DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], machineTollvm[destInst]);
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//Only add the edge if we can't verify that they do not alias
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if(AA.alias(mOp2.getVRegValue(),
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if(malias || AA.alias(mOp2.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
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mOp.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
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@ -660,7 +698,12 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, Alia
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::TrueDep);
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assert(dr.dependences.size() == 1 && "Expected at least one dependence\n");
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}
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else
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assert(dr.dependences.size() == 0 && "Expected no dependence\n");
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}
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}
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@ -668,39 +711,55 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, Alia
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for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) {
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MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
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bool malias = false;
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI->isLoad(srcNodeOpCode)) {
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//Get the Value* that we are reading from the load, always the first op
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const MachineOperand &mOp = srcInst->getOperand(0);
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assert((mOp.isUse() && (mOp.getType() == MachineOperand::MO_VirtualRegister)) && "Assumed first operand was a use and a value*\n");
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//Get the value* for the store
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const MachineOperand &mOp2 = destInst->getOperand(0);
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assert(mOp2.getType() == MachineOperand::MO_VirtualRegister && "Assumed first operand was a value*\n");
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//Only add the edge if we can't verify that they do not alias
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if(AA.alias(mOp2.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
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mOp.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
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!= AliasAnalysis::NoAlias) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep, 1);
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}
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//Get the Value* that we are reading from the load, always the first op
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const MachineOperand &mOp = srcInst->getOperand(0);
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const MachineOperand &mOp2 = destInst->getOperand(0);
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if(mOp.hasAllocatedReg())
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if(mOp.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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if(mOp2.hasAllocatedReg())
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if(mOp2.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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//Only add the edge if we can't verify that they do not alias
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if(AA.alias(mOp2.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
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mOp.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
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!= AliasAnalysis::NoAlias) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep, 1);
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}
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}
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if(TMI->isStore(srcNodeOpCode)) {
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//Get the Value* that we are reading from the store (src), always the first op
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const MachineOperand &mOp = srcInst->getOperand(0);
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assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Assumed first operand was a use and a value*\n");
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//Get the Value* that we are reading from the load, always the first op
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const MachineOperand &mOp2 = srcInst->getOperand(0);
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assert((mOp2.isUse() && (mOp2.getType() == MachineOperand::MO_VirtualRegister)) && "Assumed first operand was a use and a value*\n");
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const MachineOperand &mOp = srcInst->getOperand(0);
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const MachineOperand &mOp2 = destInst->getOperand(0);
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if(mOp.hasAllocatedReg())
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if(mOp.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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if(mOp2.hasAllocatedReg())
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if(mOp2.getReg() == SparcV9::g0)
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continue;
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else
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malias = true;
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//Only add the edge if we can't verify that they do not alias
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if(AA.alias(mOp2.getVRegValue(),
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(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
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@ -16,7 +16,7 @@
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#ifndef LLVM_MSCHEDGRAPH_H
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#define LLVM_MSCHEDGRAPH_H
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#include "DependenceAnalyzer.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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@ -241,18 +241,20 @@ namespace llvm {
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//Add Nodes and Edges to this graph for our BB
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typedef std::pair<int, MSchedGraphNode*> OpIndexNodePair;
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void buildNodesAndEdges(AliasAnalysis &AA, TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs);
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void buildNodesAndEdges(AliasAnalysis &AA, TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
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void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
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MSchedGraphNode *node,
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bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
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void addMachRegEdges(std::map<int,
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std::vector<OpIndexNodePair> >& regNumtoNodeMap);
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void addMemEdges(const std::vector<MSchedGraphNode*>& memInst, AliasAnalysis &AA, TargetData &TD);
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void addMemEdges(const std::vector<MSchedGraphNode*>& memInst, AliasAnalysis &AA, TargetData &TD,
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DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
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void addBranchEdges();
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public:
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MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ, AliasAnalysis &AA, TargetData &TD,
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std::map<const MachineInstr*, unsigned> &ignoreInstrs);
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MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ, AliasAnalysis &AA,
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TargetData &TD, std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
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//Copy constructor with maps to link old nodes to new nodes
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MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
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@ -152,6 +152,7 @@ bool ModuloSchedulingPass::runOnFunction(Function &F) {
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//Get MachineFunction
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MachineFunction &MF = MachineFunction::get(&F);
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DependenceAnalyzer &DA = getAnalysis<DependenceAnalyzer>();
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AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
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TargetData &TD = getAnalysis<TargetData>();
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@ -191,7 +192,7 @@ bool ModuloSchedulingPass::runOnFunction(Function &F) {
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continue;
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}
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MSchedGraph *MSG = new MSchedGraph(*BI, target, AA, TD, indVarInstrs[*BI]);
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MSchedGraph *MSG = new MSchedGraph(*BI, target, AA, TD, indVarInstrs[*BI], DA, machineTollvm[*BI]);
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//Write Graph out to file
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DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG));
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@ -349,7 +350,6 @@ bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) {
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if(BI->getBasicBlock()->size() == 1)
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return false;
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//Increase number of single basic block loops for stats
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++SingleBBLoops;
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@ -363,8 +363,11 @@ bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) {
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for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) {
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//Get opcode to check instruction type
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MachineOpCode OC = I->getOpcode();
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//Look for calls
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if(TMI->isCall(OC))
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return false;
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//Look for conditional move
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if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi
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|| OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
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@ -422,6 +425,15 @@ bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) {
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std::cerr << **N << "\n";
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});
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//Create map of machine instr to llvm instr
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std::map<MachineInstr*, Instruction*> mllvm;
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for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
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for (unsigned j = 0; j < tempMvec.size(); j++) {
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mllvm[tempMvec[j]] = I;
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}
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}
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//Convert list of LLVM Instructions to list of Machine instructions
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std::map<const MachineInstr*, unsigned> mIndVar;
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for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
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@ -443,7 +455,7 @@ bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) {
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//Put into a map for future access
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indVarInstrs[BI] = mIndVar;
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machineTollvm[BI] = mllvm;
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return true;
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}
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@ -1864,7 +1876,7 @@ void ModuloSchedulingPass::writePrologues(std::vector<MachineBasicBlock *> &prol
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MSchedGraphNode *branch = 0;
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MSchedGraphNode *BAbranch = 0;
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schedule.print(std::cerr);
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DEBUG(schedule.print(std::cerr));
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std::vector<MSchedGraphNode*> branches;
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@ -17,7 +17,7 @@
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#include "MSSchedule.h"
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#include "llvm/Function.h"
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#include "llvm/Pass.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "DependenceAnalyzer.h"
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#include "llvm/Target/TargetData.h"
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#include <set>
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@ -47,6 +47,9 @@ namespace llvm {
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//Map to hold list of instructions associate to the induction var for each BB
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std::map<const MachineBasicBlock*, std::map<const MachineInstr*, unsigned> > indVarInstrs;
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//Map to hold machine to llvm instrs for each valid BB
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std::map<const MachineBasicBlock*, std::map<MachineInstr*, Instruction*> > machineTollvm;
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//LLVM Instruction we know we can add TmpInstructions to its MCFI
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Instruction *defaultInst;
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@ -145,6 +148,7 @@ namespace llvm {
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// getAnalysisUsage
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DependenceAnalyzer>();
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<TargetData>();
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}
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