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ARM: Split out cost model vcvt testcases.
They had a separate RUN line already, so may as well be in a separate file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179988 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
ddb14ce76c
commit
5eabdf2601
171
test/CodeGen/ARM/vcvt-cost.ll
Normal file
171
test/CodeGen/ARM/vcvt-cost.ll
Normal file
@ -0,0 +1,171 @@
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; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8
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; instructions as expensive. If lowering is improved the cost model needs to
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; change.
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; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
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%T0_5 = type <8 x i8>
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%T1_5 = type <8 x i32>
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; CHECK: func_cvt5:
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define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
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; CHECK: vmovl.s8
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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%v0 = load %T0_5* %loadaddr
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; COST: func_cvt5
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; COST: cost of 3 {{.*}} sext
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%r = sext %T0_5 %v0 to %T1_5
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store %T1_5 %r, %T1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TA0_5 = type <8 x i8>
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%TA1_5 = type <8 x i32>
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; CHECK: func_cvt1:
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define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
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; CHECK: vmovl.u8
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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%v0 = load %TA0_5* %loadaddr
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; COST: func_cvt1
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; COST: cost of 3 {{.*}} zext
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%r = zext %TA0_5 %v0 to %TA1_5
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store %TA1_5 %r, %TA1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%T0_51 = type <8 x i32>
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%T1_51 = type <8 x i8>
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; CHECK: func_cvt51:
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define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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%v0 = load %T0_51* %loadaddr
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; COST: func_cvt51
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; COST: cost of 19 {{.*}} trunc
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%r = trunc %T0_51 %v0 to %T1_51
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store %T1_51 %r, %T1_51* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TT0_5 = type <16 x i8>
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%TT1_5 = type <16 x i32>
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; CHECK: func_cvt52:
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define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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%v0 = load %TT0_5* %loadaddr
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; COST: func_cvt52
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; COST: cost of 6 {{.*}} sext
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%r = sext %TT0_5 %v0 to %TT1_5
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store %TT1_5 %r, %TT1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TTA0_5 = type <16 x i8>
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%TTA1_5 = type <16 x i32>
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; CHECK: func_cvt12:
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define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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%v0 = load %TTA0_5* %loadaddr
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; COST: func_cvt12
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; COST: cost of 6 {{.*}} zext
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%r = zext %TTA0_5 %v0 to %TTA1_5
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store %TTA1_5 %r, %TTA1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TT0_51 = type <16 x i32>
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%TT1_51 = type <16 x i8>
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; CHECK: func_cvt512:
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define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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%v0 = load %TT0_51* %loadaddr
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; COST: func_cvt512
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; COST: cost of 38 {{.*}} trunc
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%r = trunc %TT0_51 %v0 to %TT1_51
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store %TT1_51 %r, %TT1_51* %storeaddr
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ret void
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}
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; CHECK: sext_v4i16_v4i64:
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define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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%v0 = load <4 x i16>* %loadaddr
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; COST: sext_v4i16_v4i64
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; COST: cost of 3 {{.*}} sext
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%r = sext <4 x i16> %v0 to <4 x i64>
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store <4 x i64> %r, <4 x i64>* %storeaddr
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ret void
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}
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; CHECK: zext_v4i16_v4i64:
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define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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%v0 = load <4 x i16>* %loadaddr
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; COST: zext_v4i16_v4i64
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; COST: cost of 3 {{.*}} zext
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%r = zext <4 x i16> %v0 to <4 x i64>
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store <4 x i64> %r, <4 x i64>* %storeaddr
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ret void
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}
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; CHECK: sext_v8i16_v8i64:
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define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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%v0 = load <8 x i16>* %loadaddr
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; COST: sext_v8i16_v8i64
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; COST: cost of 6 {{.*}} sext
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%r = sext <8 x i16> %v0 to <8 x i64>
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store <8 x i64> %r, <8 x i64>* %storeaddr
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ret void
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}
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; CHECK: zext_v8i16_v8i64:
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define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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%v0 = load <8 x i16>* %loadaddr
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; COST: zext_v8i16_v8i64
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; COST: cost of 6 {{.*}} zext
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%r = zext <8 x i16> %v0 to <8 x i64>
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store <8 x i64> %r, <8 x i64>* %storeaddr
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ret void
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}
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@ -156,175 +156,3 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
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declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
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; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8
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; instructions as expensive. If lowering is improved the cost model needs to
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; change.
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; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
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%T0_5 = type <8 x i8>
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%T1_5 = type <8 x i32>
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; CHECK: func_cvt5:
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define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
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; CHECK: vmovl.s8
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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%v0 = load %T0_5* %loadaddr
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; COST: func_cvt5
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; COST: cost of 3 {{.*}} sext
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%r = sext %T0_5 %v0 to %T1_5
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store %T1_5 %r, %T1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TA0_5 = type <8 x i8>
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%TA1_5 = type <8 x i32>
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; CHECK: func_cvt1:
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define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
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; CHECK: vmovl.u8
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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%v0 = load %TA0_5* %loadaddr
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; COST: func_cvt1
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; COST: cost of 3 {{.*}} zext
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%r = zext %TA0_5 %v0 to %TA1_5
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store %TA1_5 %r, %TA1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%T0_51 = type <8 x i32>
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%T1_51 = type <8 x i8>
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; CHECK: func_cvt51:
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define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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%v0 = load %T0_51* %loadaddr
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; COST: func_cvt51
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; COST: cost of 19 {{.*}} trunc
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%r = trunc %T0_51 %v0 to %T1_51
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store %T1_51 %r, %T1_51* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TT0_5 = type <16 x i8>
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%TT1_5 = type <16 x i32>
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; CHECK: func_cvt52:
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define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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; CHECK: vmovl.s16
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%v0 = load %TT0_5* %loadaddr
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; COST: func_cvt52
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; COST: cost of 6 {{.*}} sext
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%r = sext %TT0_5 %v0 to %TT1_5
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store %TT1_5 %r, %TT1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TTA0_5 = type <16 x i8>
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%TTA1_5 = type <16 x i32>
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; CHECK: func_cvt12:
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define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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; CHECK: vmovl.u16
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%v0 = load %TTA0_5* %loadaddr
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; COST: func_cvt12
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; COST: cost of 6 {{.*}} zext
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%r = zext %TTA0_5 %v0 to %TTA1_5
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store %TTA1_5 %r, %TTA1_5* %storeaddr
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ret void
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}
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;; We currently estimate the cost of this instruction as expensive. If lowering
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;; is improved the cost needs to change.
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%TT0_51 = type <16 x i32>
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%TT1_51 = type <16 x i8>
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; CHECK: func_cvt512:
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define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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; CHECK: strb
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%v0 = load %TT0_51* %loadaddr
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; COST: func_cvt512
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; COST: cost of 38 {{.*}} trunc
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%r = trunc %TT0_51 %v0 to %TT1_51
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store %TT1_51 %r, %TT1_51* %storeaddr
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ret void
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}
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; CHECK: sext_v4i16_v4i64:
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define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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%v0 = load <4 x i16>* %loadaddr
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; COST: sext_v4i16_v4i64
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; COST: cost of 3 {{.*}} sext
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%r = sext <4 x i16> %v0 to <4 x i64>
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store <4 x i64> %r, <4 x i64>* %storeaddr
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ret void
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}
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; CHECK: zext_v4i16_v4i64:
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define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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%v0 = load <4 x i16>* %loadaddr
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; COST: zext_v4i16_v4i64
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; COST: cost of 3 {{.*}} zext
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%r = zext <4 x i16> %v0 to <4 x i64>
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store <4 x i64> %r, <4 x i64>* %storeaddr
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ret void
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}
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; CHECK: sext_v8i16_v8i64:
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define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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; CHECK: vmovl.s32
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%v0 = load <8 x i16>* %loadaddr
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; COST: sext_v8i16_v8i64
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; COST: cost of 6 {{.*}} sext
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%r = sext <8 x i16> %v0 to <8 x i64>
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store <8 x i64> %r, <8 x i64>* %storeaddr
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ret void
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}
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; CHECK: zext_v8i16_v8i64:
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define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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; CHECK: vmovl.u32
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%v0 = load <8 x i16>* %loadaddr
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; COST: zext_v8i16_v8i64
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; COST: cost of 6 {{.*}} zext
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%r = zext <8 x i16> %v0 to <8 x i64>
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store <8 x i64> %r, <8 x i64>* %storeaddr
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ret void
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}
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