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Disable the load/store optimization pass for Thumb-1.
Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210789 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -265,7 +265,8 @@ bool ARMPassConfig::addInstSelector() {
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}
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bool ARMPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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// FIXME: Temporarily disabling Thumb-1 pre-RA Load/Store optimization pass
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if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
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addPass(createARMLoadStoreOptimizationPass(true));
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
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addPass(createMLxExpansionPass());
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@ -280,8 +281,11 @@ bool ARMPassConfig::addPreRegAlloc() {
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bool ARMPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createARMLoadStoreOptimizationPass());
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printAndVerify("After ARM load / store optimizer");
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// FIXME: Temporarily disabling Thumb-1 post-RA Load/Store optimization pass
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if (!getARMSubtarget().isThumb1Only()) {
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addPass(createARMLoadStoreOptimizationPass());
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printAndVerify("After ARM load / store optimizer");
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}
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if (getARMSubtarget().hasNEON())
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addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=thumbv6m-eabi -o - | FileCheck %s
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; XFAIL: *
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define void @foo(i32* %A) #0 {
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entry:
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra | FileCheck %s -check-prefix=CHECK -check-prefix=RA_GREEDY
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic | FileCheck %s -check-prefix=CHECK -check-prefix=RA_BASIC
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra | FileCheck %s
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic | FileCheck %s
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%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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@ -45,8 +45,7 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
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; CHECK: sub sp, #
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; CHECK: mov r[[R0:[0-9]+]], sp
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; RA_GREEDY: str r{{[0-9+]}}, [r[[R0]]
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; RA_BASIC: stm r[[R0]]!
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; CHECK-NOT: ldr r0, [sp
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; CHECK: mov r[[R1:[0-9]+]], sp
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; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r{{[0-9]+}}
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=thumbv6m-eabi -o - | FileCheck %s
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; XFAIL: *
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@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s
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; XFAIL: *
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@d = external global [64 x i32]
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@s = external global [64 x i32]
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