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Revert "Revert "MachineScheduler: better book-keeping for asserts.""

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This reverts commit r212109, which reverted r212088.

However, disable the assert as it's not necessary for correctness.  There are
several corner cases that the assert needed to handle better for in-order
scheduling, but none of them are incorrect scheduler behavior. The assert is
mainly there to collect good unit tests like this and ensure that the
target-independent scheduler is working as expected with the various machine
models.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212187 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2014-07-02 16:46:08 +00:00
parent 6508430c76
commit 5ee1c8f6f0
2 changed files with 40 additions and 7 deletions
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18
lib/CodeGen/MachineScheduler.cpp
View File

@ -1689,7 +1689,7 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
if (NRCycle > CurrCycle) {
#ifndef NDEBUG
MaxObservedStall = std::max(NRCycle - CurrCycle, MaxObservedStall);
MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
#endif
DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(PI->ProcResourceIdx)
@ -1953,10 +1953,12 @@ void SchedBoundary::bumpNode(SUnit *SU) {
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
unsigned PIdx = PI->ProcResourceIdx;
if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
ReservedCycles[PIdx] = isTop() ? NextCycle + PI->Cycles : NextCycle;
#ifndef NDEBUG
MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
#endif
if (isTop()) {
ReservedCycles[PIdx] =
std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles);
}
else
ReservedCycles[PIdx] = NextCycle;
}
}
}
@ -2059,8 +2061,10 @@ SUnit *SchedBoundary::pickOnlyChoice() {
}
}
for (unsigned i = 0; Available.empty(); ++i) {
assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
"permanent hazard"); (void)i;
// FIXME: Re-enable assert once PR20057 is resolved.
// assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
// "permanent hazard");
(void)i;
bumpCycle(CurrCycle + 1);
releasePending();
}

29
test/CodeGen/AArch64/arm64-misched-basic-A53.ll
View File

@ -172,3 +172,32 @@ entry:
}
declare void @llvm.trap()
; Regression test for PR20057: "permanent hazard"'
; Resource contention on LDST.
; CHECK: ********** MI Scheduling **********
; CHECK: testLdStConflict
; CHECK: *** Final schedule for BB#1 ***
; CHECK: LD4Fourv2d
; CHECK: STRQui
; CHECK: ********** INTERVALS **********
define void @testLdStConflict() {
entry:
br label %loop
loop:
%0 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8* null)
%ptr = bitcast i8* undef to <2 x i64>*
store <2 x i64> zeroinitializer, <2 x i64>* %ptr, align 4
%ptr1 = bitcast i8* undef to <2 x i64>*
store <2 x i64> zeroinitializer, <2 x i64>* %ptr1, align 4
%ptr2 = bitcast i8* undef to <2 x i64>*
store <2 x i64> zeroinitializer, <2 x i64>* %ptr2, align 4
%ptr3 = bitcast i8* undef to <2 x i64>*
store <2 x i64> zeroinitializer, <2 x i64>* %ptr3, align 4
%ptr4 = bitcast i8* undef to <2 x i64>*
store <2 x i64> zeroinitializer, <2 x i64>* %ptr4, align 4
br label %loop
}
declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8*)