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[ARM] Use the efficient version of BitVector::set and a static_assert.

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No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257766 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2016-01-14 14:33:04 +00:00
parent 10387d22ff
commit 5f2bc6c766
1 changed files with 2 additions and 3 deletions
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5
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -167,9 +167,8 @@ getReservedRegs(const MachineFunction &MF) const {
Reserved.set(ARM::R9);
// Reserve D16-D31 if the subtarget doesn't support them.
if (!STI.hasVFP3() || STI.hasD16()) {
assert(ARM::D31 == ARM::D16 + 15);
for (unsigned i = 0; i != 16; ++i)
Reserved.set(ARM::D16 + i);
static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
Reserved.set(ARM::D16, ARM::D31 + 1);
}
const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)