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add more condition codes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-09-02 20:24:25 +00:00
parent a3a68bde21
commit 5f450d2948
3 changed files with 63 additions and 5 deletions
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30
lib/Target/ARM/ARM.h
View File

@ -23,16 +23,42 @@ namespace llvm {
// Enums corresponding to ARM condition codes
namespace ARMCC {
enum CondCodes {
EQ,
NE,
EQ
CS,
CC,
MI,
PL,
VS,
VC,
HI,
LS,
GE,
LT,
GT,
LE,
AL
};
}
static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
default: assert(0 && "Unknown condition code");
case ARMCC::NE: return "ne";
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::CS: return "cs";
case ARMCC::CC: return "cc";
case ARMCC::MI: return "mi";
case ARMCC::PL: return "pl";
case ARMCC::VS: return "vs";
case ARMCC::VC: return "vc";
case ARMCC::HI: return "hi";
case ARMCC::LS: return "ls";
case ARMCC::GE: return "ge";
case ARMCC::LT: return "lt";
case ARMCC::GT: return "gt";
case ARMCC::LE: return "le";
case ARMCC::AL: return "al";
}
}

2
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -89,6 +89,8 @@ static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
default: assert(0 && "Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGE: return ARMCC::GE;
case ISD::SETUGE: return ARMCC::CS;
}
}

36
test/CodeGen/ARM/branch.ll
View File

@ -1,7 +1,37 @@
; RUN: llvm-as < %s | llc -march=arm
void %f(int %a, int* %v) {
; RUN: llvm-as < %s | llc -march=arm &&
; RUN: llvm-as < %s | llc -march=arm | grep bne &&
; RUN: llvm-as < %s | llc -march=arm | grep bge &&
; RUN: llvm-as < %s | llc -march=arm | grep bcs
void %f1(int %a, int %b, int* %v) {
entry:
%tmp = seteq int %a, 0 ; <bool> [#uses=1]
%tmp = seteq int %a, %b ; <bool> [#uses=1]
br bool %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
store int 0, int* %v
ret void
return: ; preds = %entry
ret void
}
void %f2(int %a, int %b, int* %v) {
entry:
%tmp = setlt int %a, %b ; <bool> [#uses=1]
br bool %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
store int 0, int* %v
ret void
return: ; preds = %entry
ret void
}
void %f3(uint %a, uint %b, int* %v) {
entry:
%tmp = setlt uint %a, %b ; <bool> [#uses=1]
br bool %tmp, label %cond_true, label %return
cond_true: ; preds = %entry