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Fix the ARM IIC_iCMPsi itinerary and add an important assert.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2011-01-04 00:32:57 +00:00
parent a1cb585384
commit 6018deefe8
2 changed files with 3 additions and 1 deletions
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3
lib/Target/ARM/ARMScheduleA9.td
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@ -123,7 +123,8 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
[1, 1], [A9_LdBypass, A9_LdBypass]>,
InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_ALU0, A9_ALU1]>],
InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>],
[1, 1], [A9_LdBypass, NoBypass]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>],

1
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -240,6 +240,7 @@ void ARMSubtarget::computeIssueWidth() {
// clear the lowest bit
allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
}
assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
}
bool ARMSubtarget::enablePostRAScheduler(