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Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register

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moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-15 21:04:54 +00:00
parent a4c3c8f28d
commit 60396975be
2 changed files with 9 additions and 8 deletions
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15
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -1573,8 +1573,7 @@ static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
} }
// A7.5.1 // A7.5.1
#if 0 static APInt VFPExpandImm(unsigned char byte, unsigned N) {
static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
assert(N == 32 || N == 64); assert(N == 32 || N == 64);
uint64_t Result; uint64_t Result;
@ -1593,9 +1592,8 @@ static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
else else
Result |= 0x1L << 62; Result |= 0x1L << 62;
} }
return Result; return APInt(N, Result);
} }
#endif
// VFP Unary Format Instructions: // VFP Unary Format Instructions:
// //
@ -1972,10 +1970,11 @@ static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Extract/decode the f64/f32 immediate. // Extract/decode the f64/f32 immediate.
if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
&& !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
// The asm syntax specifies the before-expanded <imm>. // The asm syntax specifies the floating point value, not the 8-bit literal.
// Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
// Opcode == ARM::FCONSTD ? 64 : 32) Opcode == ARM::FCONSTD ? 64 : 32);
MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0))); MI.addOperand(MCOperand::CreateFPImm(APFloat(immRaw, true)));
++OpIdx; ++OpIdx;
} }

2
test/MC/Disassembler/neon-tests.txt
View File

@ -51,3 +51,5 @@
# CHECK: vtbx.8 d18, {d4, d5, d6}, d7 # CHECK: vtbx.8 d18, {d4, d5, d6}, d7
0x47 0x2a 0xf4 0xf3 0x47 0x2a 0xf4 0xf3
# CHECK: vmov.f32 s0, #5.000000e-01
0x00 0x0a 0xb6 0xee