mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-11 23:16:20 +00:00
AMDGPU: Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252675 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
259b76dfea
commit
6178878323
@ -285,22 +285,7 @@ SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
|
|||||||
return N;
|
return N;
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned selectVectorRegClassID(unsigned NumVectorElts, bool UseVGPR) {
|
static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
|
||||||
if (UseVGPR) {
|
|
||||||
switch (NumVectorElts) {
|
|
||||||
case 1:
|
|
||||||
return AMDGPU::VGPR_32RegClassID;
|
|
||||||
case 2:
|
|
||||||
return AMDGPU::VReg_64RegClassID;
|
|
||||||
case 4:
|
|
||||||
return AMDGPU::VReg_128RegClassID;
|
|
||||||
case 8:
|
|
||||||
return AMDGPU::VReg_256RegClassID;
|
|
||||||
case 16:
|
|
||||||
return AMDGPU::VReg_512RegClassID;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (NumVectorElts) {
|
switch (NumVectorElts) {
|
||||||
case 1:
|
case 1:
|
||||||
return AMDGPU::SReg_32RegClassID;
|
return AMDGPU::SReg_32RegClassID;
|
||||||
@ -350,23 +335,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
|
|||||||
EVT EltVT = VT.getVectorElementType();
|
EVT EltVT = VT.getVectorElementType();
|
||||||
assert(EltVT.bitsEq(MVT::i32));
|
assert(EltVT.bitsEq(MVT::i32));
|
||||||
if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
|
if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
|
||||||
bool UseVReg = false;
|
RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
|
||||||
|
|
||||||
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
|
|
||||||
U != E; ++U) {
|
|
||||||
if (!U->isMachineOpcode()) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
|
|
||||||
if (!RC) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
|
|
||||||
UseVReg = false;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
RegClassID = selectVectorRegClassID(NumVectorElts, UseVReg);
|
|
||||||
} else {
|
} else {
|
||||||
// BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
|
// BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
|
||||||
// that adds a 128 bits reg copy when going through TwoAddressInstructions
|
// that adds a 128 bits reg copy when going through TwoAddressInstructions
|
||||||
|
Loading…
x
Reference in New Issue
Block a user