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[DAGCombiner] Slightly improve readability of matchRotateSub

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Slightly change the wording in the function comment. Originally, it can be
misunderstood as we turned the input into two subsequent rotates.

Better connect the comment which talks about Mask and the code which used
LoBits.  Renamed variable to MaskLoBits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203314 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-03-07 23:56:24 +00:00
parent aa5b17b359
commit 622f350944
1 changed files with 9 additions and 8 deletions
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15
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3414,9 +3414,9 @@ static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
// //
// (or (shift1 X, Neg), (shift2 X, Pos)) // (or (shift1 X, Neg), (shift2 X, Pos))
// //
// reduces to a rotate in direction shift2 by Pos and a rotate in direction // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
// shift1 by Neg. The range [0, OpSize) means that we only need to consider // in direction shift1 by Neg. The range [0, OpSize) means that we only need
// shift amounts with defined behavior. // to consider shift amounts with defined behavior.
static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) { static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
// If OpSize is a power of 2 then: // If OpSize is a power of 2 then:
// //
@ -3449,13 +3449,13 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
// always invokes undefined behavior for 32-bit X. // always invokes undefined behavior for 32-bit X.
// //
// Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise. // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
unsigned LoBits = 0; unsigned MaskLoBits = 0;
if (Neg.getOpcode() == ISD::AND && if (Neg.getOpcode() == ISD::AND &&
isPowerOf2_64(OpSize) && isPowerOf2_64(OpSize) &&
Neg.getOperand(1).getOpcode() == ISD::Constant && Neg.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) { cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
Neg = Neg.getOperand(0); Neg = Neg.getOperand(0);
LoBits = Log2_64(OpSize); MaskLoBits = Log2_64(OpSize);
} }
// Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1. // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
@ -3496,8 +3496,9 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
return false; return false;
// Now we just need to check that OpSize & Mask == Width & Mask. // Now we just need to check that OpSize & Mask == Width & Mask.
if (LoBits) if (MaskLoBits)
return Width.getLoBits(LoBits) == 0; // Opsize & Mask is 0 since Mask is Opsize - 1.
return Width.getLoBits(MaskLoBits) == 0;
return Width == OpSize; return Width == OpSize;
} }