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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183491 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,13 +37,11 @@ static cl::opt<bool> MBDisableDelaySlotFiller(
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namespace {
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struct Filler : public MachineFunctionPass {
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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: MachineFunctionPass(ID), TM(tm) { }
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virtual const char *getPassName() const {
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return "MBlaze Delay Slot Filler";
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@ -239,7 +237,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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Changed = true;
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if (D == MBB.end())
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BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(MBlaze::NOP));
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BuildMI(MBB, ++J, I->getDebugLoc(),TM.getInstrInfo()->get(MBlaze::NOP));
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else
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MBB.splice(++J, &MBB, D);
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}
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@ -29,7 +29,7 @@ using namespace llvm;
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MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
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: MBlazeGenInstrInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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TM(tm), RI(*TM.getSubtargetImpl()) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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@ -42,8 +42,8 @@
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using namespace llvm;
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MBlazeRegisterInfo::
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MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
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: MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
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MBlazeRegisterInfo(const MBlazeSubtarget &ST)
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: MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST) {}
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unsigned MBlazeRegisterInfo::getPICCallReg() {
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return MBlaze::R20;
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@ -37,10 +37,8 @@ namespace MBlaze {
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struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
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const MBlazeSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget,
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const TargetInstrInfo &tii);
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MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget);
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/// Get PIC indirect call register
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static unsigned getPICCallReg();
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