RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-14 15:39:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Clean up uses of TargetLowering::getTargetMachine.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-04 15:39:15 +00:00
parent ef7803217a
commit 6448d91ad1
5 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3452,7 +3452,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
LoadSDNode *LD = cast<LoadSDNode>(LD1);
unsigned Align = LD->getAlignment();
unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
unsigned NewAlign = TLI.getTargetData()->
getABITypeAlignment(VT.getTypeForMVT());
if (NewAlign <= Align &&
(!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT)))
@ -3507,7 +3507,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
!cast<LoadSDNode>(N0)->isVolatile() &&
(!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
unsigned Align = TLI.getTargetData()->
getABITypeAlignment(VT.getTypeForMVT());
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
@ -4611,7 +4611,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
ST->isUnindexed()) {
unsigned Align = ST->getAlignment();
MVT SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
unsigned OrigAlign = TLI.getTargetData()->
getABITypeAlignment(SVT.getTypeForMVT());
if (Align <= OrigAlign &&
((!AfterLegalize && !ST->isVolatile()) ||
@ -4842,7 +4842,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
if (NewLoad) {
// Check the resultant load doesn't need a higher alignment than the
// original load.
unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
unsigned NewAlign = TLI.getTargetData()->
getABITypeAlignment(LVT.getTypeForMVT());
if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
return SDValue();

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -302,7 +302,7 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
}
const TargetMachine &SelectionDAG::getTarget() const {
return TLI.getTargetMachine();
return MF->getTarget();
}
//===----------------------------------------------------------------------===//

2
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -310,7 +310,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
MVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
PHIReg += NumRegisters;

2
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -327,7 +327,7 @@ public:
/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
/// this target when scheduling the DAG.
virtual HazardRecognizer *CreateTargetHazardRecognizer() {
const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
const TargetInstrInfo *II = TM.getInstrInfo();
assert(II && "No InstrInfo?");
return new SPUHazardRecognizer(*II);
}

2
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -187,7 +187,7 @@ namespace {
virtual HazardRecognizer *CreateTargetHazardRecognizer() {
// Should use subtarget info to pick the right hazard recognizer. For
// now, always return a PPC970 recognizer.
const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
const TargetInstrInfo *II = TM.getInstrInfo();
assert(II && "No InstrInfo?");
return new PPCHazardRecognizer970(*II);
}