RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-13 06:39:12 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

constify accessor.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-05-21 17:47:50 +00:00
parent 19f5f71bba
commit 65569b8ddf
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -216,7 +216,8 @@ public:
/// getRegClassVirtRegs - Return the list of virtual registers of the given
/// target register class.
std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
const std::vector<unsigned> &
getRegClassVirtRegs(const TargetRegisterClass *RC) const {
return RegClass2VRegMap[RC->getID()];
}

2
lib/CodeGen/PreAllocSplitting.cpp
View File

@ -1154,7 +1154,7 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
// codegen is not modelling. Ignore these barriers for now.
if (!TII->isSafeToMoveRegClassDefs(*RC))
continue;
std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
const std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
unsigned Reg = VRs[i];
if (!LIs->hasInterval(Reg))