From 6583fa2beceedcf751df4c89d1a2c46eab2b2b23 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 22 Sep 2018 05:16:35 +0000 Subject: [PATCH] [X86] Fix inline expansion for memset in x32 Summary: Similar to D51893 which was for memcpy Reviewers: efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52063 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342796 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrCompiler.td | 54 ++++++++++++++++---------- lib/Target/X86/X86SelectionDAGInfo.cpp | 5 ++- test/CodeGen/X86/pr38865-3.ll | 18 +++++++++ 3 files changed, 54 insertions(+), 23 deletions(-) create mode 100644 test/CodeGen/X86/pr38865-3.ll diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index 657757a5ffe..111dc28f2eb 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -434,37 +434,49 @@ def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), // FIXME: Should use "(X86rep_stos AL)" as the pattern. let Defs = [ECX,EDI], isCodeGenOnly = 1 in { let Uses = [AL,ECX,EDI] in - def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", - [(X86rep_stos i8)]>, REP, - Requires<[Not64BitMode]>; + def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), + "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", + [(X86rep_stos i8)]>, REP, AdSize32, + Requires<[NotLP64]>; let Uses = [AX,ECX,EDI] in - def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", - [(X86rep_stos i16)]>, REP, OpSize16, - Requires<[Not64BitMode]>; + def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), + "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", + [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, + Requires<[NotLP64]>; let Uses = [EAX,ECX,EDI] in - def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", - [(X86rep_stos i32)]>, REP, OpSize32, - Requires<[Not64BitMode]>; + def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), + "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", + [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, + Requires<[NotLP64]>; + let Uses = [RAX,RCX,RDI] in + def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), + "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", + [(X86rep_stos i64)]>, REP, AdSize32, + Requires<[NotLP64, In64BitMode]>; } let Defs = [RCX,RDI], isCodeGenOnly = 1 in { let Uses = [AL,RCX,RDI] in - def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", - [(X86rep_stos i8)]>, REP, - Requires<[In64BitMode]>; + def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), + "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", + [(X86rep_stos i8)]>, REP, AdSize64, + Requires<[IsLP64]>; let Uses = [AX,RCX,RDI] in - def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", - [(X86rep_stos i16)]>, REP, OpSize16, - Requires<[In64BitMode]>; + def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), + "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", + [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, + Requires<[IsLP64]>; let Uses = [RAX,RCX,RDI] in - def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", - [(X86rep_stos i32)]>, REP, OpSize32, - Requires<[In64BitMode]>; + def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), + "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", + [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, + Requires<[IsLP64]>; let Uses = [RAX,RCX,RDI] in - def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", - [(X86rep_stos i64)]>, REP, - Requires<[In64BitMode]>; + def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), + "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", + [(X86rep_stos i64)]>, REP, AdSize64, + Requires<[IsLP64]>; } } // SchedRW diff --git a/lib/Target/X86/X86SelectionDAGInfo.cpp b/lib/Target/X86/X86SelectionDAGInfo.cpp index eb861cebd57..a71e5d39595 100644 --- a/lib/Target/X86/X86SelectionDAGInfo.cpp +++ b/lib/Target/X86/X86SelectionDAGInfo.cpp @@ -170,10 +170,11 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset( InFlag = Chain.getValue(1); } - Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, + bool Use64BitRegs = Subtarget.isTarget64BitLP64(); + Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX, Count, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, + Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI, Dst, InFlag); InFlag = Chain.getValue(1); diff --git a/test/CodeGen/X86/pr38865-3.ll b/test/CodeGen/X86/pr38865-3.ll new file mode 100644 index 00000000000..c4d9ece4c2d --- /dev/null +++ b/test/CodeGen/X86/pr38865-3.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -show-mc-encoding < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnux32" + +define void @foo(i8* %x) optsize { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $707406378, %eax # encoding: [0xb8,0x2a,0x2a,0x2a,0x2a] +; CHECK-NEXT: # imm = 0x2A2A2A2A +; CHECK-NEXT: movl $32, %ecx # encoding: [0xb9,0x20,0x00,0x00,0x00] +; CHECK-NEXT: rep;stosl %eax, %es:(%edi) # encoding: [0xf3,0x67,0xab] +; CHECK-NEXT: retq # encoding: [0xc3] + call void @llvm.memset.p0i8.i32(i8* align 4 %x, i8 42, i32 128, i1 false) + ret void +} +declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i1)