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Implement SHL_PARTS and SRL_PARTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23072 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1184,6 +1184,44 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->ReplaceAllUsesWith(N, Result);
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return Result[Op.ResNo];
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}
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case ISD::SHL_PARTS: {
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SDOperand HI = Select(N->getOperand(0));
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SDOperand LO = Select(N->getOperand(1));
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SDOperand SH = Select(N->getOperand(2));
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SDOperand SH_LO_R = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, SH,
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getI32Imm(32));
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SDOperand SH_LO_L = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH,
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getI32Imm((unsigned)-32));
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SDOperand HI_SHL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH);
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SDOperand HI_LOR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH_LO_R);
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SDOperand HI_LOL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH_LO_L);
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SDOperand HI_OR = CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_SHL, HI_LOR);
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std::vector<SDOperand> Result;
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Result.push_back(CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH));
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Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_OR, HI_LOL));
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CurDAG->ReplaceAllUsesWith(N, Result);
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return Result[Op.ResNo];
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}
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case ISD::SRL_PARTS: {
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SDOperand HI = Select(N->getOperand(0));
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SDOperand LO = Select(N->getOperand(1));
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SDOperand SH = Select(N->getOperand(2));
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SDOperand SH_HI_L = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, SH,
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getI32Imm(32));
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SDOperand SH_HI_R = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH,
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getI32Imm((unsigned)-32));
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SDOperand LO_SHR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH);
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SDOperand LO_HIL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH_HI_L);
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SDOperand LO_HIR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH_HI_R);
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SDOperand LO_OR = CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_SHR, LO_HIL);
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std::vector<SDOperand> Result;
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Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_OR, LO_HIR));
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Result.push_back(CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH));
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CurDAG->ReplaceAllUsesWith(N, Result);
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return Result[Op.ResNo];
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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