RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-24 20:30:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fixing warnings caused by commit 323095

Browse Source 
Change-Id: I4e1f81db2f5382a820f4016c23b243e4d5aebf51

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323114 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marina Yatsina 2018-01-22 13:24:10 +00:00
parent efadeb465e
commit 66bd7d7663
3 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/ExecutionDomainFix.cpp
View File

@ -167,7 +167,7 @@ void ExecutionDomainFix::enterBasicBlock(
// Try to coalesce live-out registers from predecessors.
for (MachineBasicBlock *pred : MBB->predecessors()) {
assert(pred->getNumber() < MBBOutRegsInfos.size() &&
assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
"Should have pre-allocated MBBInfos for all MBBs");
LiveRegsDVInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
// Incoming is null if this is a backedge from a BB
@ -208,7 +208,7 @@ void ExecutionDomainFix::enterBasicBlock(
void ExecutionDomainFix::leaveBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
assert(!LiveRegs.empty() && "Must enter basic block first.");
int MBBNumber = TraversedMBB.MBB->getNumber();
unsigned MBBNumber = TraversedMBB.MBB->getNumber();
assert(MBBNumber < MBBOutRegsInfos.size() &&
"Unexpected basic block number.");
// Save register clearances at end of MBB - used by enterBasicBlock().

6
lib/CodeGen/LoopTraversal.cpp
View File

@ -14,7 +14,7 @@
using namespace llvm;
bool LoopTraversal::isBlockDone(MachineBasicBlock *MBB) {
int MBBNumber = MBB->getNumber();
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number.");
return MBBInfos[MBBNumber].PrimaryCompleted &&
MBBInfos[MBBNumber].IncomingCompleted ==
@ -33,7 +33,7 @@ LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) {
for (MachineBasicBlock *MBB : RPOT) {
// N.B: IncomingProcessed and IncomingCompleted were already updated while
// processing this block's predecessors.
int MBBNumber = MBB->getNumber();
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number.");
MBBInfos[MBBNumber].PrimaryCompleted = true;
MBBInfos[MBBNumber].PrimaryIncoming = MBBInfos[MBBNumber].IncomingProcessed;
@ -45,7 +45,7 @@ LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) {
bool Done = isBlockDone(ActiveMBB);
MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done));
for (MachineBasicBlock *Succ : ActiveMBB->successors()) {
int SuccNumber = Succ->getNumber();
unsigned SuccNumber = Succ->getNumber();
assert(SuccNumber < MBBInfos.size() &&
"Unexpected basic block number.");
if (!isBlockDone(Succ)) {

10
lib/CodeGen/ReachingDefAnalysis.cpp
View File

@ -23,7 +23,7 @@ void ReachingDefAnalysis::enterBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
MachineBasicBlock *MBB = TraversedMBB.MBB;
int MBBNumber = MBB->getNumber();
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBReachingDefs.size() &&
"Unexpected basic block number.");
MBBReachingDefs[MBBNumber].resize(NumRegUnits);
@ -53,7 +53,7 @@ void ReachingDefAnalysis::enterBasicBlock(
// Try to coalesce live-out registers from predecessors.
for (MachineBasicBlock *pred : MBB->predecessors()) {
assert(pred->getNumber() < MBBOutRegsInfos.size() &&
assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
"Should have pre-allocated MBBInfos for all MBBs");
const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
// Incoming is null if this is a backedge from a BB
@ -77,7 +77,7 @@ void ReachingDefAnalysis::enterBasicBlock(
void ReachingDefAnalysis::leaveBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
assert(!LiveRegs.empty() && "Must enter basic block first.");
int MBBNumber = TraversedMBB.MBB->getNumber();
unsigned MBBNumber = TraversedMBB.MBB->getNumber();
assert(MBBNumber < MBBOutRegsInfos.size() &&
"Unexpected basic block number.");
// Save register clearances at end of MBB - used by enterBasicBlock().
@ -95,7 +95,7 @@ void ReachingDefAnalysis::leaveBasicBlock(
void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
assert(!MI->isDebugValue() && "Won't process debug values");
int MBBNumber = MI->getParent()->getNumber();
unsigned MBBNumber = MI->getParent()->getNumber();
assert(MBBNumber < MBBReachingDefs.size() &&
"Unexpected basic block number.");
const MCInstrDesc &MCID = MI->getDesc();
@ -174,7 +174,7 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
assert(InstIds.count(MI) && "Unexpected machine instuction.");
int InstId = InstIds[MI];
int DefRes = ReachingDedDefaultVal;
int MBBNumber = MI->getParent()->getNumber();
unsigned MBBNumber = MI->getParent()->getNumber();
assert(MBBNumber < MBBReachingDefs.size() &&
"Unexpected basic block number.");
int LatestDef = ReachingDedDefaultVal;