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80 col violation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50266 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-04-25 17:21:40 +00:00
parent 280a6e607d
commit 682f81032f
1 changed files with 1 additions and 1 deletions
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2
lib/Target/TargetRegisterInfo.cpp
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@ -54,7 +54,7 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg,
// Pick the register class of the right type that contains this physreg. // Pick the register class of the right type that contains this physreg.
SmallVector<const TargetRegisterClass*, 4> RCs; SmallVector<const TargetRegisterClass*, 4> RCs;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) { for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg)) if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg))
RCs.push_back(*I); RCs.push_back(*I);
} }