diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 334d75fd534..05c3859b4b9 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3714,7 +3714,8 @@ def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
   let Inst{3-0}   = Rn;
 }
 
-let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
+let Constraints =
+    "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
                 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
                               4, IIC_iMAC64, [],
diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll
index 2cf91c32bc1..a7ecbf808ed 100644
--- a/test/CodeGen/ARM/longMAC.ll
+++ b/test/CodeGen/ARM/longMAC.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=CHECK-V7
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
@@ -42,3 +43,28 @@ define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
   %add = add nsw i64 %mul, %conv2
   ret i64 %add
 }
+
+; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.
+;    + Without @earlyclobber the v7 code is natural. With it, the first two
+;      registers must be distinct from the third.
+;    + Without "$Rd = $R", this can be satisfied without a mov before the umlal
+;      by trying to use 6 different registers in the MachineInstr. The natural
+;      evolution of this attempt currently leaves only two movs in the final
+;      function, both after the umlal. With it, *some* move has to happen
+;      before the umlal.
+define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) {
+; CHECK-V7-LABEL: MACLongTest5:
+; CHECK-V7-LABEL: umlal r0, r1, r0, r0
+
+; CHECK-LABEL: MACLongTest5:
+; CHECK: mov [[RDLO:r[0-9]+]], r0
+; CHECK: umlal [[RDLO]], r1, r0, r0
+; CHECK: mov r0, [[RDLO]]
+
+  %conv.trunc = trunc i64 %c to i32
+  %conv = zext i32 %conv.trunc to i64
+  %conv1 = zext i32 %b to i64
+  %mul = mul i64 %conv, %conv
+  %add = add i64 %mul, %c
+  ret i64 %add
+}