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fix an oversight which caused us to compile the testcase (and other

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less trivial things) into a dummy lea.  Before we generated:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	ret

now we produce:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	ret

This is part of rdar://9289558



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129662 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2011-04-17 17:12:08 +00:00
parent dceb52a01b
commit 685090f598
3 changed files with 22 additions and 9 deletions
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8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -421,10 +421,9 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
return true; return true;
} }
void void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, BasicBlock::const_iterator End,
BasicBlock::const_iterator End, bool &HadTailCall) {
bool &HadTailCall) {
// Lower all of the non-terminator instructions. If a call is emitted // Lower all of the non-terminator instructions. If a call is emitted
// as a tail call, cease emitting nodes for this block. Terminators // as a tail call, cease emitting nodes for this block. Terminators
// are handled below. // are handled below.
@ -438,7 +437,6 @@ SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
// Final step, emit the lowered DAG as machine code. // Final step, emit the lowered DAG as machine code.
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
return;
} }
void SelectionDAGISel::ComputeLiveOutVRegInfo() { void SelectionDAGISel::ComputeLiveOutVRegInfo() {

11
lib/Target/X86/X86FastISel.cpp
View File

@ -1859,10 +1859,13 @@ unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
if (isa<GlobalValue>(C)) { if (isa<GlobalValue>(C)) {
X86AddressMode AM; X86AddressMode AM;
if (X86SelectAddress(C, AM)) { if (X86SelectAddress(C, AM)) {
if (TLI.getPointerTy() == MVT::i32) // If the expression is just a basereg, then we're done, otherwise we need
Opc = X86::LEA32r; // to emit an LEA.
else if (AM.BaseType == X86AddressMode::RegBase &&
Opc = X86::LEA64r; AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
return AM.Base.Reg;
Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
unsigned ResultReg = createResultReg(RC); unsigned ResultReg = createResultReg(RC);
addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg), AM); TII.get(Opc), ResultReg), AM);

12
test/CodeGen/X86/fast-isel-x86-64.ll
View File

@ -33,3 +33,15 @@ if.end: ; preds = %if.then, %entry
; CHECK: test2: ; CHECK: test2:
; CHECK: movq %rdi, -8(%rsp) ; CHECK: movq %rdi, -8(%rsp)
; CHECK: cmpq $42, -8(%rsp) ; CHECK: cmpq $42, -8(%rsp)
@G = external global i32
define i64 @test3() nounwind {
%A = ptrtoint i32* @G to i64
ret i64 %A
}
; CHECK: test3:
; CHECK: movq _G@GOTPCREL(%rip), %rax
; CHECK-NEXT: ret