RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-01 15:40:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

initial support for branches

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-08-24 13:45:55 +00:00
parent 3bca110dc3
commit 687bc49d1a
4 changed files with 43 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -174,8 +174,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
O << "#" << (int)MO.getImmedValue();
break;
case MachineOperand::MO_MachineBasicBlock:
assert(0 && "not implemented");
abort();
printBasicBlockLabel(MO.getMachineBasicBlock());
return;
case MachineOperand::MO_GlobalAddress: {
GlobalValue *GV = MO.getGlobal();

21
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -53,6 +53,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setSchedulingPreference(SchedulingForRegPressure);
computeRegisterProperties();
@ -71,7 +72,9 @@ namespace llvm {
CMP,
SELECT
SELECT,
BR
};
}
}
@ -83,6 +86,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
case ARMISD::SELECT: return "ARMISD::SELECT";
case ARMISD::CMP: return "ARMISD::CMP";
case ARMISD::BR: return "ARMISD::BR";
}
}
@ -312,6 +316,19 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4);
assert(CC == ISD::SETNE);
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, Cmp);
}
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default:
@ -329,6 +346,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return LowerRET(Op, DAG);
case ISD::SELECT_CC:
return LowerSELECT_CC(Op, DAG);
case ISD::BR_CC:
return LowerBR_CC(Op, DAG);
}
}

9
lib/Target/ARM/ARMInstrInfo.td
View File

@ -37,6 +37,8 @@ class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Pattern = pattern;
}
def brtarget : Operand<OtherVT>;
def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
[SDNPHasChain, SDNPOutFlag]>;
@ -50,6 +52,9 @@ def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>;
def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
def SDTarmbr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
@ -107,6 +112,10 @@ let isTwoAddress = 1 in {
[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
}
def bne : InstARM<(ops brtarget:$dst),
"bne $dst",
[(armbr bb:$dst)]>;
def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
"cmp $a, $b",
[(armcmp IntRegs:$a, IntRegs:$b)]>;

13
test/CodeGen/ARM/branch.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc -march=arm
void %f(int %a, int* %v) {
entry:
%tmp = seteq int %a, 0 ; <bool> [#uses=1]
br bool %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
store int 0, int* %v
ret void
return: ; preds = %entry
ret void
}