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make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48118 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-09 20:12:44 +00:00
parent 4c55c633d9
commit 68a0d0984d
1 changed files with 5 additions and 3 deletions
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8
lib/Target/IA64/IA64RegisterInfo.td
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@ -418,8 +418,9 @@ def GR : RegisterClass<"IA64", [i64], 64,
r96, r97, r98, r99, r100, r101, r102, r103, r96, r97, r98, r99, r100, r101, r102, r103,
r104, r105, r106, r107, r108, r109, r110, r111, r104, r105, r106, r107, r108, r109, r110, r111,
r112, r113, r114, r115, r116, r117, r118, r119, r112, r113, r114, r115, r116, r117, r118, r119,
// last 17 are special (look down)
r120, r121, r122, r123, r124, r125, r126, r127, r120, r121, r122, r123, r124, r125, r126, r127,
r0, r1, r2, r5, r12, r13, r22, rp]> // last 16 are special (look down) r0, r1, r2, r5, r12, r13, r22, rp, AR_PFS]>
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_begin(const MachineFunction &MF) const;
@ -434,8 +435,9 @@ def GR : RegisterClass<"IA64", [i64], 64,
GRClass::iterator GRClass::iterator
GRClass::allocation_order_end(const MachineFunction &MF) const { GRClass::allocation_order_end(const MachineFunction &MF) const {
int numReservedRegs=8;// the 8 special registers r0,r1,r2,r5,r12,r13 etc // the 9 special registers r0,r1,r2,r5,r12,r13 etc
int numReservedRegs=9;
// we also can't allocate registers for use as locals if they're already // we also can't allocate registers for use as locals if they're already
// required as 'out' registers // required as 'out' registers
numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;