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[FastISel][AArch64] Add target-specific lowering for logical operations.
This change adds support for immediate and shift-left folding into logical operations. This fixes rdar://problem/18223183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217118 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
fa2dfaedf2
commit
68a4ab08b3
@ -114,6 +114,7 @@ class AArch64FastISel : public FastISel {
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private:
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// Selection routines.
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bool selectAddSub(const Instruction *I);
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bool selectLogicalOp(const Instruction *I);
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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@ -193,7 +194,14 @@ private:
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unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
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bool WantResult = true);
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unsigned emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
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const Value *RHS);
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unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, uint64_t Imm);
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unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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uint64_t ShiftImm);
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unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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@ -1222,22 +1230,83 @@ unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
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WantResult);
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}
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// FIXME: This should be eventually generated automatically by tblgen.
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unsigned AArch64FastISel::emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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uint64_t Imm) {
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const TargetRegisterClass *RC = nullptr;
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unsigned Opc = 0;
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unsigned RegSize = 0;
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unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
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const Value *LHS, const Value *RHS) {
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if (RetVT != MVT::i32 && RetVT != MVT::i64)
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return 0;
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// Canonicalize immediates to the RHS first.
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if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
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std::swap(LHS, RHS);
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// Canonicalize shift immediate to the RHS.
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if (isValueAvailable(LHS))
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if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
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if (isa<ConstantInt>(SI->getOperand(1)))
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if (SI->getOpcode() == Instruction::Shl)
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std::swap(LHS, RHS);
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unsigned LHSReg = getRegForValue(LHS);
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if (!LHSReg)
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return 0;
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bool LHSIsKill = hasTrivialKill(LHS);
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unsigned ResultReg = 0;
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if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
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uint64_t Imm = C->getZExtValue();
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ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
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}
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if (ResultReg)
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return ResultReg;
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// Check if the shift can be folded into the instruction.
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if (isValueAvailable(RHS))
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if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
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if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
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if (SI->getOpcode() == Instruction::Shl) {
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uint64_t ShiftVal = C->getZExtValue();
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unsigned RHSReg = getRegForValue(SI->getOperand(0));
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if (!RHSReg)
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return 0;
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bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
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return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
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RHSIsKill, ShiftVal);
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}
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unsigned RHSReg = getRegForValue(RHS);
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if (!RHSReg)
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return 0;
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bool RHSIsKill = hasTrivialKill(RHS);
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return fastEmit_rr(RetVT, RetVT, ISDOpc, LHSReg, LHSIsKill, RHSReg,
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RHSIsKill);
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}
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unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
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unsigned LHSReg, bool LHSIsKill,
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uint64_t Imm) {
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assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
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"ISD nodes are not consecutive!");
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static const unsigned OpcTable[3][2] = {
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{ AArch64::ANDWri, AArch64::ANDXri },
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{ AArch64::ORRWri, AArch64::ORRXri },
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{ AArch64::EORWri, AArch64::EORXri }
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};
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const TargetRegisterClass *RC;
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unsigned Opc;
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unsigned RegSize;
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switch (RetVT.SimpleTy) {
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default:
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return 0;
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case MVT::i32:
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Opc = AArch64::ANDWri;
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case MVT::i32: {
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unsigned Idx = ISDOpc - ISD::AND;
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Opc = OpcTable[Idx][0];
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RC = &AArch64::GPR32spRegClass;
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RegSize = 32;
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break;
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}
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case MVT::i64:
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Opc = AArch64::ANDXri;
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Opc = OpcTable[ISDOpc - ISD::AND][1];
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RC = &AArch64::GPR64spRegClass;
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RegSize = 64;
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break;
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@ -1250,6 +1319,40 @@ unsigned AArch64FastISel::emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
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}
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unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
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unsigned LHSReg, bool LHSIsKill,
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unsigned RHSReg, bool RHSIsKill,
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uint64_t ShiftImm) {
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assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
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"ISD nodes are not consecutive!");
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static const unsigned OpcTable[3][2] = {
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{ AArch64::ANDWrs, AArch64::ANDXrs },
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{ AArch64::ORRWrs, AArch64::ORRXrs },
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{ AArch64::EORWrs, AArch64::EORXrs }
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};
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const TargetRegisterClass *RC;
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unsigned Opc;
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switch (RetVT.SimpleTy) {
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default:
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return 0;
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case MVT::i32:
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Opc = OpcTable[ISDOpc - ISD::AND][0];
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RC = &AArch64::GPR32RegClass;
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break;
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case MVT::i64:
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Opc = OpcTable[ISDOpc - ISD::AND][1];
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RC = &AArch64::GPR64RegClass;
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break;
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}
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return fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
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}
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unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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uint64_t Imm) {
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return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
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}
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bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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@ -1316,7 +1419,7 @@ bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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// Loading an i1 requires special handling.
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if (VTIsi1) {
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unsigned ANDReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
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unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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ResultReg = ANDReg;
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}
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@ -1341,6 +1444,34 @@ bool AArch64FastISel::selectAddSub(const Instruction *I) {
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return true;
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}
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bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
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MVT VT;
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if (!isTypeSupported(I->getType(), VT))
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return false;
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unsigned ISDOpc;
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switch (I->getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode.");
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case Instruction::And:
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ISDOpc = ISD::AND;
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break;
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case Instruction::Or:
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ISDOpc = ISD::OR;
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break;
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case Instruction::Xor:
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ISDOpc = ISD::XOR;
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break;
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}
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unsigned ResultReg =
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emitLogicalOp(ISDOpc, VT, I->getOperand(0), I->getOperand(1));
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if (!ResultReg)
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool AArch64FastISel::SelectLoad(const Instruction *I) {
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MVT VT;
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// Verify we have a legal type before going any further. Currently, we handle
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@ -1423,7 +1554,7 @@ bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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// Storing an i1 requires special handling.
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if (VTIsi1 && SrcReg != AArch64::WZR) {
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unsigned ANDReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
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unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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SrcReg = ANDReg;
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}
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@ -1576,7 +1707,7 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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CondIsKill = true;
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}
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unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
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unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
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@ -1750,7 +1881,7 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
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bool CondIsKill = hasTrivialKill(Cond);
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if (NeedTest) {
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unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
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unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
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}
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@ -2721,7 +2852,7 @@ bool AArch64FastISel::SelectTrunc(const Instruction *I) {
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unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
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AArch64::sub_32);
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// Create the AND instruction which performs the actual truncation.
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ResultReg = emitAND_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
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ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
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assert(ResultReg && "Unexpected AND instruction emission failure.");
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} else {
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ResultReg = createResultReg(&AArch64::GPR32RegClass);
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@ -2743,7 +2874,7 @@ unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
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DestVT = MVT::i32;
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if (isZExt) {
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unsigned ResultReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
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unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
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assert(ResultReg && "Unexpected AND instruction emission failure.");
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if (DestVT == MVT::i64) {
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// We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
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@ -2823,13 +2954,13 @@ unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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if (NeedTrunc) {
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Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op1IsKill = true;
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}
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unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
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Op1IsKill);
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if (NeedTrunc)
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ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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return ResultReg;
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}
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@ -2916,14 +3047,14 @@ unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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if (NeedTrunc) {
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Op0Reg = emitAND_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
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Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
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Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op0IsKill = Op1IsKill = true;
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}
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unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
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Op1IsKill);
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if (NeedTrunc)
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ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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return ResultReg;
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}
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@ -3026,13 +3157,13 @@ unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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if (NeedTrunc) {
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Op0Reg = EmitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
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Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
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Op0IsKill = Op1IsKill = true;
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}
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unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
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Op1IsKill);
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if (NeedTrunc)
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ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
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return ResultReg;
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}
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@ -3470,11 +3601,17 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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return selectBinaryOp(I, ISD::SRA);
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return true;
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case Instruction::And:
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return selectBinaryOp(I, ISD::AND);
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::AND);
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return true;
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case Instruction::Or:
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return selectBinaryOp(I, ISD::OR);
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::OR);
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return true;
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case Instruction::Xor:
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return selectBinaryOp(I, ISD::XOR);
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::XOR);
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return true;
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case Instruction::GetElementPtr:
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return selectGetElementPtr(I);
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case Instruction::Br:
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@ -137,11 +137,10 @@ declare void @foo1()
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; rdar://15174028
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define i32 @trunc64(i64 %foo) nounwind {
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; CHECK: trunc64
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0x1
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; CHECK: and [[REG2:x[0-9]+]], x0, [[REG]]
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; CHECK: mov x[[REG3:[0-9]+]], [[REG2]]
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; CHECK: and [[REG4:w[0-9]+]], w[[REG3]], #0x1
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; CHECK: cmp [[REG4]], #0
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; CHECK: and [[REG1:x[0-9]+]], x0, #0x1
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; CHECK: mov x[[REG2:[0-9]+]], [[REG1]]
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; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0x1
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; CHECK: cmp [[REG3]], #0
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; CHECK: b.eq LBB5_2
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%a = and i64 %foo, 1
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%b = trunc i64 %a to i1
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@ -23,9 +23,8 @@ entry:
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; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
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; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
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; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
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; CHECK: orr [[REG8:x[0-9]+]], xzr, #0xffff
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; CHECK: and [[REG9:x[0-9]+]], [[REG7]], [[REG8]]
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; CHECK: str [[REG9]], {{\[}}[[REG1]]{{\]}}
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; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
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; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}
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; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
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%0 = load i64* @seed, align 8
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%mul = mul nsw i64 %0, 1309
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138
test/CodeGen/AArch64/fast-isel-logic-op.ll
Normal file
138
test/CodeGen/AArch64/fast-isel-logic-op.ll
Normal file
@ -0,0 +1,138 @@
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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; AND
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define i32 @and_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rr_i32
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; CHECK: and w0, w0, w1
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%1 = and i32 %a, %b
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ret i32 %1
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}
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define i64 @and_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rr_i64
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; CHECK: and x0, x0, x1
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%1 = and i64 %a, %b
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ret i64 %1
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}
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define i32 @and_ri_i32(i32 %a) {
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; CHECK-LABEL: and_ri_i32
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||||
; CHECK: and w0, w0, #0xff
|
||||
%1 = and i32 %a, 255
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @and_ri_i64(i64 %a) {
|
||||
; CHECK-LABEL: and_ri_i64
|
||||
; CHECK: and x0, x0, #0xff
|
||||
%1 = and i64 %a, 255
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @and_rs_i32(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: and_rs_i32
|
||||
; CHECK: and w0, w0, w1, lsl #8
|
||||
%1 = shl i32 %b, 8
|
||||
%2 = and i32 %a, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @and_rs_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: and_rs_i64
|
||||
; CHECK: and x0, x0, x1, lsl #8
|
||||
%1 = shl i64 %b, 8
|
||||
%2 = and i64 %a, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
; OR
|
||||
define i32 @or_rr_i32(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: or_rr_i32
|
||||
; CHECK: orr w0, w0, w1
|
||||
%1 = or i32 %a, %b
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @or_rr_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: or_rr_i64
|
||||
; CHECK: orr x0, x0, x1
|
||||
%1 = or i64 %a, %b
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @or_ri_i32(i32 %a) {
|
||||
; CHECK-LABEL: or_ri_i32
|
||||
; CHECK: orr w0, w0, #0xff
|
||||
%1 = or i32 %a, 255
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @or_ri_i64(i64 %a) {
|
||||
; CHECK-LABEL: or_ri_i64
|
||||
; CHECK: orr x0, x0, #0xff
|
||||
%1 = or i64 %a, 255
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @or_rs_i32(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: or_rs_i32
|
||||
; CHECK: orr w0, w0, w1, lsl #8
|
||||
%1 = shl i32 %b, 8
|
||||
%2 = or i32 %a, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @or_rs_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: or_rs_i64
|
||||
; CHECK: orr x0, x0, x1, lsl #8
|
||||
%1 = shl i64 %b, 8
|
||||
%2 = or i64 %a, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
; XOR
|
||||
define i32 @xor_rr_i32(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: xor_rr_i32
|
||||
; CHECK: eor w0, w0, w1
|
||||
%1 = xor i32 %a, %b
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @xor_rr_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: xor_rr_i64
|
||||
; CHECK: eor x0, x0, x1
|
||||
%1 = xor i64 %a, %b
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @xor_ri_i32(i32 %a) {
|
||||
; CHECK-LABEL: xor_ri_i32
|
||||
; CHECK: eor w0, w0, #0xff
|
||||
%1 = xor i32 %a, 255
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @xor_ri_i64(i64 %a) {
|
||||
; CHECK-LABEL: xor_ri_i64
|
||||
; CHECK: eor x0, x0, #0xff
|
||||
%1 = xor i64 %a, 255
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @xor_rs_i32(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: xor_rs_i32
|
||||
; CHECK: eor w0, w0, w1, lsl #8
|
||||
%1 = shl i32 %b, 8
|
||||
%2 = xor i32 %a, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @xor_rs_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: xor_rs_i64
|
||||
; CHECK: eor x0, x0, x1, lsl #8
|
||||
%1 = shl i64 %b, 8
|
||||
%2 = xor i64 %a, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user