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add a big table with target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117230 91177308-0d34-0410-b5e6-96231b3b80d8
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Chris Lattner
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@ -92,6 +92,7 @@
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<li><a href="#targetimpls">Target-specific Implementation Notes</a>
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<ul>
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<li><a href="#targetfeatures">Target Feature Matrix</a></li>
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<li><a href="#tailcallopt">Tail call optimization</a></li>
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<li><a href="#sibcallopt">Sibling call optimization</a></li>
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<li><a href="#x86">The X86 backend</a></li>
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@ -1900,10 +1901,282 @@ compiler.</p>
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<div class="doc_text">
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<p>This section of the document explains features or design decisions that are
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specific to the code generator for a particular target.</p>
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specific to the code generator for a particular target. First we start
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with a table that summarizes what features are supported by each target.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="targetfeatures">Target Feature Matrix</a>
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</div>
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<style type="text/css">
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.unknown { background-color: #C0C0C0; text-align: center; }
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.unknown:before { content: "?" }
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.no { background-color: #C11B17 }
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.no:before { content: "N" }
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.partial { background-color: #F88017 }
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.yes { background-color: #00FF00; }
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.yes:before { content: "Y" }
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</style>
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<div class="doc_text">
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<p>Note that this table does not include the C backend or Cpp backends, since
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they do not use the target independent code generator infrastructure. It also
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doesn't list features that are not supported fully by any target yet. It
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considers a feature to be supported if at least one subtarget supports it. A
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feature being supported means that it is useful and works for most cases, it
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does not indicate that there are zero known bugs in the implementation. Here
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is the key:</p>
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<table border="1" cellspacing="0">
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<tr>
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<th>Unknown</th>
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<th>No support</th>
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<th>Partial Support</th>
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<th>Complete Support</th>
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</tr>
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<tr>
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<td class="unknown"></td>
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<td class="no"></td>
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<td class="partial"></td>
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<td class="yes"></td>
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</tr>
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</table>
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<p>Here is the table:</p>
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<table width="689" border="1" cellspacing="0">
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<tr><td></td>
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<td colspan="13" align="center" bgcolor="#ffffcc">Target</td>
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</tr>
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<tr>
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<th>Feature</th>
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<th>ARM</th>
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<th>Alpha</th>
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<th>Blackfin</th>
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<th>CellSPU</th>
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<th>MBlaze</th>
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<th>MSP430</th>
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<th>Mips</th>
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<th>PTX</th>
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<th>PowerPC</th>
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<th>Sparc</th>
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<th>SystemZ</th>
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<th>X86</th>
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<th>XCore</th>
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</tr>
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<tr>
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<td><a href="#feat_reliable">is generally reliable</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="unknown"></td> <!-- Blackfin -->
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<td class="unknown"></td> <!-- CellSPU -->
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<td class="unknown"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="unknown"></td> <!-- Mips -->
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<td class="no"></td> <!-- PTX -->
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<td class="yes"></td> <!-- PowerPC -->
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<td class="yes"></td> <!-- Sparc -->
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<td class="unknown"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="unknown"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_asmparser">assembly parser</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- Blackfin -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
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<td class="no"></td> <!-- PTX -->
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<td class="no"></td> <!-- PowerPC -->
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<td class="no"></td> <!-- Sparc -->
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<td class="no"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="no"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_disassembler">disassembler</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- Blackfin -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
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<td class="no"></td> <!-- PTX -->
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<td class="no"></td> <!-- PowerPC -->
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<td class="no"></td> <!-- Sparc -->
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<td class="no"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="no"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_inlineasm">inline asm</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="unknown"></td> <!-- Blackfin -->
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<td class="unknown"></td> <!-- CellSPU -->
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<td class="unknown"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="unknown"></td> <!-- Mips -->
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<td class="unknown"></td> <!-- PTX -->
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<td class="yes"></td> <!-- PowerPC -->
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<td class="unknown"></td> <!-- Sparc -->
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<td class="unknown"></td> <!-- SystemZ -->
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<td class="yes"><a href="#feat_inlineasm_x86">*</a></td> <!-- X86 -->
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<td class="unknown"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_jit">jit</a></td>
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<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="unknown"></td> <!-- Blackfin -->
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<td class="unknown"></td> <!-- CellSPU -->
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<td class="unknown"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="unknown"></td> <!-- Mips -->
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<td class="unknown"></td> <!-- PTX -->
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<td class="yes"></td> <!-- PowerPC -->
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<td class="unknown"></td> <!-- Sparc -->
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<td class="unknown"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="unknown"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_objectwrite">.o file writing</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- Blackfin -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
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<td class="no"></td> <!-- PTX -->
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<td class="no"></td> <!-- PowerPC -->
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<td class="no"></td> <!-- Sparc -->
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<td class="no"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="no"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_tailcall">tail calls</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="unknown"></td> <!-- Blackfin -->
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<td class="unknown"></td> <!-- CellSPU -->
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<td class="unknown"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="unknown"></td> <!-- Mips -->
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<td class="unknown"></td> <!-- PTX -->
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<td class="yes"></td> <!-- PowerPC -->
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<td class="unknown"></td> <!-- Sparc -->
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<td class="unknown"></td> <!-- SystemZ -->
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<td class="yes"></td> <!-- X86 -->
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<td class="unknown"></td> <!-- XCore -->
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</tr>
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</table>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_reliable">Is Generally Reliable</div>
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<div class="doc_text">
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<p>This box indicates whether the target is considered to be production quality.
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This indicates that the target has been used as a static compiler to
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compile large amounts of code by a variety of different people and is in
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continuous use.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_asmparser">Assembly Parser</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports parsing target specific .s
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files by implementing the MCAsmParser interface. This is required for llvm-mc
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to be able to act as a native assembler and is required for inline assembly
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support in the native .o file writer.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_disassembler">Disassembler</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports the MCDisassembler API for
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disassembling machine opcode bytes into MCInst's.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_inlineasm">Inline Asm</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports most popular inline assembly
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constraints and modifiers.</p>
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<p id="feat_inlineasm_x86">X86 lacks reliable support for inline assembly
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constraints relating to the X86 floating point stack.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_jit">JIT Support</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports the JIT compiler through
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the ExecutionEngine interface.</p>
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<p id="feat_inlineasm_arm">The ARM backend has basic support for integer code
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in ARM codegen mode, but lacks NEON and full Thumb support.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_objectwrite">.o File Writing</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports writing .o files (e.g. MachO,
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ELF, and/or COFF) files directly from the target. Note that the target also
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must include an assembly parser and general inline assembly support for full
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inline assembly support in the .o writer.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection" id="feat_tailcall">Tail Calls</div>
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<div class="doc_text">
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<p>This box indicates whether the target supports guaranteed tail calls. These
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are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
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calling convention. Please see the <a href="#tailcallopt">tail call section
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more more details</a>.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="tailcallopt">Tail call optimization</a>
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