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Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects

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that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-07 01:56:04 +00:00
parent 6425f8be72
commit 69244300b8
31 changed files with 154 additions and 226 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/MachineInstr.h
View File

@ -68,9 +68,9 @@ public:
const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }
/// getInstrDescriptor - Returns the target instruction descriptor of this
/// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
const TargetInstrDescriptor *getDesc() const { return TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///

93
include/llvm/Target/TargetInstrInfo.h
View File

@ -191,6 +191,31 @@ public:
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
bool isCall() const {
return Flags & M_CALL_FLAG;
}
bool isBranch() const {
return Flags & M_BRANCH_FLAG;
}
bool isTerminator() const {
return Flags & M_TERMINATOR_FLAG;
}
bool isIndirectBranch() const {
return Flags & M_INDIRECT_FLAG;
}
bool isPredicable() const {
return Flags & M_PREDICABLE;
}
bool isNotDuplicable() const {
return Flags & M_NOT_DUPLICABLE;
}
/// isSimpleLoad - Return true for instructions that are simple loads from
/// memory. This should only be set on instructions that load a value from
@ -201,6 +226,26 @@ public:
return Flags & M_SIMPLE_LOAD_FLAG;
}
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore() const {
return Flags & M_MAY_STORE_FLAG;
}
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.
bool isBarrier() const {
return Flags & M_BARRIER_FLAG;
}
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot() const {
return Flags & M_DELAY_SLOT_FLAG;
}
};
@ -274,42 +319,6 @@ public:
bool isCommutableInstr(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_COMMUTABLE;
}
bool isTerminatorInstr(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
bool isBranch(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_BRANCH_FLAG;
}
bool isIndirectBranch(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_INDIRECT_FLAG;
}
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.
bool isBarrier(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_BARRIER_FLAG;
}
bool isCall(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_CALL_FLAG;
}
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_MAY_STORE_FLAG;
}
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
}
/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
@ -322,14 +331,6 @@ public:
return get(Opcode).Flags & M_VARIABLE_OPS;
}
bool isPredicable(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_PREDICABLE;
}
bool isNotDuplicable(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_NOT_DUPLICABLE;
}
bool hasOptionalDef(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
}
@ -338,7 +339,7 @@ public:
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
bool isTriviallyReMaterializable(MachineInstr *MI) const {
return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
isReallyTriviallyReMaterializable(MI);
}
@ -346,7 +347,7 @@ public:
/// effects that are not captured by any operands of the instruction or other
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
return !isReallySideEffectFree(MI); // May have side effects

25
lib/CodeGen/BranchFolding.cpp
View File

@ -346,14 +346,13 @@ MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
/// EstimateRuntime - Make a rough estimate for how long it will take to run
/// the specified code.
static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
MachineBasicBlock::iterator E,
const TargetInstrInfo *TII) {
MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
if (TID.Flags & M_CALL_FLAG)
const TargetInstrDescriptor *TID = I->getDesc();
if (TID->isCall())
Time += 10;
else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG))
else if (TID->isSimpleLoad() || TID->mayStore())
Time += 2;
else
++Time;
@ -368,7 +367,6 @@ static bool ShouldSplitFirstBlock(MachineBasicBlock *MBB1,
MachineBasicBlock::iterator MBB1I,
MachineBasicBlock *MBB2,
MachineBasicBlock::iterator MBB2I,
const TargetInstrInfo *TII,
MachineBasicBlock *PredBB) {
// If one block is the entry block, split the other one; we can't generate
// a branch to the entry block, as its label is not emitted.
@ -389,8 +387,8 @@ static bool ShouldSplitFirstBlock(MachineBasicBlock *MBB1,
// TODO: if we had some notion of which block was hotter, we could split
// the hot block, so it is the fall-through. Since we don't have profile info
// make a decision based on which will hurt most to split.
unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I, TII);
unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I, TII);
unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I);
unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I);
// If the MBB1 prefix takes "less time" to run than the MBB2 prefix, split the
// MBB1 block so it falls through. This will penalize the MBB2 path, but will
@ -544,7 +542,7 @@ bool BranchFolder::TryMergeBlocks(MachineBasicBlock *SuccBB,
}
// Decide whether we want to split CurMBB or MBB2.
if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, TII, PredBB)) {
if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, PredBB)) {
CurMBB = SplitMBBAt(*CurMBB, BBI1);
BBI1 = CurMBB->begin();
MergePotentials.back().second = CurMBB;
@ -766,8 +764,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) {
/// a strict ordering, returning true for both (MBB1,MBB2) and (MBB2,MBB1) will
/// result in infinite loops.
static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
MachineBasicBlock *MBB2,
const TargetInstrInfo &TII) {
MachineBasicBlock *MBB2) {
// Right now, we use a simple heuristic. If MBB2 ends with a call, and
// MBB1 doesn't, we prefer to fall through into MBB1. This allows us to
// optimize branches that branch to either a return block or an assert block
@ -781,7 +778,7 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
return TII.isCall(MBB2I->getOpcode()) && !TII.isCall(MBB1I->getOpcode());
return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
@ -894,7 +891,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// last. Only do the swap if one is clearly better to fall through than
// the other.
if (FallThrough == --MBB->getParent()->end() &&
!IsBetterFallthrough(PriorTBB, MBB, *TII))
!IsBetterFallthrough(PriorTBB, MBB))
DoTransform = false;
// We don't want to do this transformation if we have control flow like:
@ -961,7 +958,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
TII->isBranch(MBB->begin()->getOpcode()) && CurTBB != MBB) {
MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.

2
lib/CodeGen/Collector.cpp
View File

@ -359,7 +359,7 @@ void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {
BBE = MF.end(); BBI != BBE; ++BBI)
for (MachineBasicBlock::iterator MI = BBI->begin(),
ME = BBI->end(); MI != ME; ++MI)
if (TII->isCall(MI->getOpcode()))
if (MI->getDesc()->isCall())
VisitCallPoint(*MI);
}

4
lib/CodeGen/DwarfWriter.cpp
View File

@ -3147,15 +3147,13 @@ private:
// Whether the last callsite entry was for an invoke.
bool PreviousIsInvoke = false;
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Visit all instructions in order of address.
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (MI->getOpcode() != TargetInstrInfo::LABEL) {
SawPotentiallyThrowing |= TII->isCall(MI->getOpcode());
SawPotentiallyThrowing |= MI->getDesc()->isCall();
continue;
}

18
lib/CodeGen/IfConversion.cpp
View File

@ -462,8 +462,7 @@ MachineBasicBlock::iterator firstNonBranchInst(MachineBasicBlock *BB,
MachineBasicBlock::iterator I = BB->end();
while (I != BB->begin()) {
--I;
const TargetInstrDescriptor *TID = I->getInstrDescriptor();
if ((TID->Flags & M_BRANCH_FLAG) == 0)
if (!I->getDesc()->isBranch())
break;
}
return I;
@ -522,7 +521,7 @@ bool IfConverter::ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
/// ScanInstructions - Scan all the instructions in the block to determine if
/// the block is predicable. In most cases, that means all the instructions
/// in the block has M_PREDICABLE flag. Also checks if the block contains any
/// in the block are isPredicable(). Also checks if the block contains any
/// instruction which can clobber a predicate (e.g. condition code register).
/// If so, the block is not predicable unless it's the last instruction.
void IfConverter::ScanInstructions(BBInfo &BBI) {
@ -551,13 +550,12 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
bool SeenCondBr = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
const TargetInstrDescriptor *TID = I->getInstrDescriptor();
if ((TID->Flags & M_NOT_DUPLICABLE) != 0)
const TargetInstrDescriptor *TID = I->getDesc();
if (TID->isNotDuplicable())
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
bool isCondBr = BBI.IsBrAnalyzable &&
(TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0;
bool isCondBr = BBI.IsBrAnalyzable && TID->isBranch() && !TID->isBarrier();
if (!isCondBr) {
if (!isPredicated)
@ -594,7 +592,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
if (TII->DefinesPredicate(I, PredDefs))
BBI.ClobbersPred = true;
if ((TID->Flags & M_PREDICABLE) == 0) {
if (!TID->isPredicable()) {
BBI.IsUnpredicable = true;
return;
}
@ -1136,10 +1134,10 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
bool IgnoreBr) {
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
const TargetInstrDescriptor *TID = I->getInstrDescriptor();
const TargetInstrDescriptor *TID = I->getDesc();
bool isPredicated = TII->isPredicated(I);
// Do not copy the end of the block branches.
if (IgnoreBr && !isPredicated && (TID->Flags & M_BRANCH_FLAG) != 0)
if (IgnoreBr && !isPredicated && TID->isBranch())
break;
MachineInstr *MI = I->clone();

14
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -615,7 +615,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
return false;
isLoad = false;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
tii_->isTriviallyReMaterializable(MI)) {
isLoad = TID->isSimpleLoad();
@ -680,7 +680,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
unsigned MRInfo = 0;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
if (TID->Flags & M_IMPLICIT_DEF_FLAG) {
RemoveMachineInstrFromMaps(MI);
@ -1226,7 +1226,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
(DefIsReMat && (ReMatDefMI->getInstrDescriptor()->isSimpleLoad()));
(DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
@ -1308,7 +1308,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
(DefIsReMat && ReMatDefMI->getInstrDescriptor()->isSimpleLoad());
(DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
@ -1423,7 +1423,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
if (isLoadSS || ReMatDefMI->getInstrDescriptor()->isSimpleLoad())
if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
}
@ -1451,8 +1451,8 @@ addIntervalsForSpills(const LiveInterval &li,
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
assert(UseIdx != -1);
if (LastUse->getInstrDescriptor()->
getOperandConstraint(UseIdx, TOI::TIED_TO) == -1) {
if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
-1) {
LastUse->getOperand(UseIdx).setIsKill();
vrm.addKillPoint(LI->reg, LastUseIdx);
}

7
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -131,11 +131,10 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
}
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
const TargetInstrInfo& TII = *getParent()->getTarget().getInstrInfo();
iterator I = end();
while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode()))
while (I != begin() && (--I)->getDesc()->isTerminator())
; /*noop */
if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I;
if (I != end() && !I->getDesc()->isTerminator()) ++I;
return I;
}
@ -262,7 +261,7 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
MachineBasicBlock::iterator I = end();
while (I != begin()) {
--I;
if (!(I->getInstrDescriptor()->Flags & M_TERMINATOR_FLAG)) break;
if (!I->getDesc()->isTerminator()) break;
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.

14
lib/CodeGen/MachineInstr.cpp
View File

@ -288,7 +288,7 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB,
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
TID = MI.getInstrDescriptor();
TID = MI.getDesc();
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
@ -538,8 +538,8 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
const TargetInstrDescriptor *TID = getInstrDescriptor();
if (TID->Flags & M_PREDICABLE) {
const TargetInstrDescriptor *TID = getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
return i;
@ -551,7 +551,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
const TargetInstrDescriptor *TID = getInstrDescriptor();
const TargetInstrDescriptor *TID = getDesc();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
@ -588,8 +588,8 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_PREDICABLE) {
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
// Predicated operands must be last operands.
@ -612,7 +612,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
++StartOp; // Don't print this operand again!
}
OS << getInstrDescriptor()->Name;
OS << getDesc()->Name;
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
if (i != StartOp)

14
lib/CodeGen/MachineLICM.cpp
View File

@ -225,23 +225,21 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
DEBUG({
DOUT << "--- Checking if we can hoist " << I;
if (I.getInstrDescriptor()->ImplicitUses) {
if (I.getDesc()->ImplicitUses) {
DOUT << " * Instruction has implicit uses:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
const unsigned *ImpUses = I.getInstrDescriptor()->ImplicitUses;
for (; *ImpUses; ++ImpUses)
for (const unsigned *ImpUses = I.getDesc()->ImplicitUses;
*ImpUses; ++ImpUses)
DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
}
if (I.getInstrDescriptor()->ImplicitDefs) {
if (I.getDesc()->ImplicitDefs) {
DOUT << " * Instruction has implicit defines:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
const unsigned *ImpDefs = I.getInstrDescriptor()->ImplicitDefs;
for (; *ImpDefs; ++ImpDefs)
for (const unsigned *ImpDefs = I.getDesc()->ImplicitDefs;
*ImpDefs; ++ImpDefs)
DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
}

2
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -269,7 +269,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = I;
while (I2 != MBB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
I = I2;
bool AtStart = I == MBB->begin();

5
lib/CodeGen/RegAllocSimple.cpp
View File

@ -173,8 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const TargetInstrDescriptor &Desc = *MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
@ -204,7 +203,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
int TiedOp = MI->getDesc()->findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {

6
lib/CodeGen/RegisterScavenging.cpp
View File

@ -95,7 +95,7 @@ void RegScavenger::forward() {
// Reaching a terminator instruction. Restore a scavenged register (which
// must be life out.
if (TII->isTerminatorInstr(MI->getOpcode()))
if (MI->getDesc()->isTerminator())
restoreScavengedReg();
// Process uses first.
@ -122,7 +122,7 @@ void RegScavenger::forward() {
setUnused(ChangedRegs);
// Process defs.
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
@ -152,7 +152,7 @@ void RegScavenger::backward() {
MachineInstr *MI = MBBI;
// Process defs first.
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())

2
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -433,7 +433,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
bool isOptDef = (IIOpNum < TID->numOperands)
? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));

4
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -35,8 +35,8 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const {
bool MadeChange = false;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_PREDICABLE) {
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->isPredicable()) {
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);

2
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -93,7 +93,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) {
const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
const TargetInstrDescriptor *TID = mi->getDesc();
bool FirstTied = true;
for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {

6
lib/CodeGen/VirtRegMap.cpp
View File

@ -537,7 +537,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I,
/// over.
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
std::vector<MachineOperand*> &KillOps) {
const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
const TargetInstrDescriptor *TID = MI.getDesc();
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || !MO.isUse())
@ -966,7 +966,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
NextMII = next(MII);
MachineInstr &MI = *MII;
const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
const TargetInstrDescriptor *TID = MI.getDesc();
// Insert restores here if asked to.
if (VRM.isRestorePt(&MI)) {
@ -1436,7 +1436,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
int TiedOp = MI.getDesc()->findTiedToSrcOperand(i);
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {

4
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -201,8 +201,8 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
const unsigned opcode = MI.getOpcode();
const TargetInstrDescriptor *Desc = MI.getDesc();
unsigned opcode = Desc->Opcode;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;

4
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -371,7 +371,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
if (TII->isBranch(Opc)) {
if (I->getDesc()->isBranch()) {
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
@ -423,7 +423,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
unsigned TSFlags = I->getInstrDescriptor()->TSFlags;
unsigned TSFlags = I->getDesc()->TSFlags;
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.

12
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -63,7 +63,7 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
return true;
case ARM::MOVr:
case ARM::tMOVr:
assert(MI.getInstrDescriptor()->numOperands >= 2 &&
assert(MI.getDesc()->numOperands >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
@ -180,7 +180,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
return NULL;
MachineInstr *MI = MBBI;
unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
unsigned TSFlags = MI->getDesc()->TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
@ -200,7 +200,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
unsigned NumOps = TID->numOperands;
bool isLoad = TID->isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
@ -837,7 +837,7 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
return false;
@ -870,7 +870,7 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MI->getDesc();
unsigned TSFlags = TID->TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
@ -899,7 +899,7 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
// jumptable. The size is 4 + 4 * number of entries.
unsigned NumOps = TID->numOperands;
MachineOperand JTOP =
MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -599,7 +599,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
const TargetInstrDescriptor *TID = MBBI->getDesc();
unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;

4
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -581,7 +581,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
unsigned Opcode = MI.getOpcode();
const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
const TargetInstrDescriptor &Desc = *MI.getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
@ -797,7 +797,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
else // tLDR has an extra register operand.
MI.addOperand(MachineOperand::CreateReg(0, false));
} else if (TII.mayStore(Opcode)) {
} else if (Desc.mayStore()) {
// FIXME! This is horrific!!! We need register scavenging.
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
// also a ABI register so it's possible that is is the register that is

2
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -59,7 +59,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB)
{
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
if (TII->hasDelaySlot(I->getOpcode())) {
if (I->getDesc()->hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(Mips::NOP));

2
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -175,7 +175,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (!isBranch(LastInst->getOpcode()))
if (!LastInst->getDesc()->isBranch())
return true;
// Unconditional branch

5
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -256,7 +256,8 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
UpdatedVRSAVE).addReg(InVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
@ -267,7 +268,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = IP;
while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
IP = I2;
// Emit: MTVRSAVE InVRSave

2
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -65,7 +65,7 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
if (TII->hasDelaySlot(I->getOpcode())) {
if (I->getDesc()->hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(SP::NOP));

19
lib/Target/TargetInstrInfo.cpp
View File

@ -38,14 +38,13 @@ TargetInstrInfo::~TargetInstrInfo() {
}
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_TERMINATOR_FLAG) {
// Conditional branch is a special case.
if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
return true;
if ((TID->Flags & M_PREDICABLE) == 0)
return true;
return !isPredicated(MI);
}
return false;
const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->isTerminator()) return false;
// Conditional branch is a special case.
if (TID->isBranch() && !TID->isBarrier())
return true;
if (!TID->isPredicable())
return true;
return !isPredicated(MI);
}

4
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -115,7 +115,7 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
const TargetInstrDescriptor *Desc = I->getInstrDescriptor();
const TargetInstrDescriptor *Desc = I->getDesc();
emitInstruction(*I, Desc);
// MOVPC32r is basically a call plus a pop instruction.
if (Desc->Opcode == X86::MOVPC32r)
@ -436,7 +436,7 @@ inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
/// size, and 3) use of X86-64 extended registers.
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
const TargetInstrDescriptor *Desc = MI.getDesc();
// Pseudo instructions do not need REX prefix byte.
if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)

10
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -205,7 +205,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
unsigned Flags = MI->getInstrDescriptor()->TSFlags;
unsigned Flags = MI->getDesc()->TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
@ -597,7 +597,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned NumOps = MI->getInstrDescriptor()->numOperands;
unsigned NumOps = MI->getDesc()->numOperands;
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
@ -657,7 +657,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned NumOps = MI->getInstrDescriptor()->numOperands;
unsigned NumOps = MI->getDesc()->numOperands;
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
@ -766,7 +766,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
unsigned NumOperands = MI->getDesc()->numOperands;
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@ -864,7 +864,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
unsigned NumOperands = MI->getDesc()->numOperands;
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));

23
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1243,16 +1243,15 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
}
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_TERMINATOR_FLAG) {
// Conditional branch is a special case.
if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
return true;
if ((TID->Flags & M_PREDICABLE) == 0)
return true;
return !isPredicated(MI);
}
return false;
const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->isTerminator()) return false;
// Conditional branch is a special case.
if (TID->isBranch() && !TID->isBarrier())
return true;
if (!TID->isPredicable())
return true;
return !isPredicated(MI);
}
// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
@ -1277,7 +1276,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
if (!isBranch(LastInst->getOpcode()))
if (!LastInst->getDesc()->isBranch())
return true;
// If the block ends with a branch there are 3 possibilities:
@ -1695,7 +1694,7 @@ X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
bool isTwoAddrFold = false;
unsigned NumOps = getNumOperands(MI->getOpcode());
bool isTwoAddr = NumOps > 1 &&
MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address

65
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -139,68 +139,6 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
}
}
static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
MachineOperand &MO) {
if (MO.isRegister())
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
false, false, MO.getSubReg());
else if (MO.isImmediate())
MIB = MIB.addImm(MO.getImm());
else if (MO.isFrameIndex())
MIB = MIB.addFrameIndex(MO.getIndex());
else if (MO.isGlobalAddress())
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
else if (MO.isConstantPoolIndex())
MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
else if (MO.isJumpTableIndex())
MIB = MIB.addJumpTableIndex(MO.getIndex());
else if (MO.isExternalSymbol())
MIB = MIB.addExternalSymbol(MO.getSymbolName());
else
assert(0 && "Unknown operand for X86InstrAddOperand!");
return MIB;
}
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
unsigned StackAlign) {
unsigned Opc = 0;
if (RC == &X86::GR64RegClass) {
Opc = X86::MOV64mr;
} else if (RC == &X86::GR32RegClass) {
Opc = X86::MOV32mr;
} else if (RC == &X86::GR16RegClass) {
Opc = X86::MOV16mr;
} else if (RC == &X86::GR8RegClass) {
Opc = X86::MOV8mr;
} else if (RC == &X86::GR32_RegClass) {
Opc = X86::MOV32_mr;
} else if (RC == &X86::GR16_RegClass) {
Opc = X86::MOV16_mr;
} else if (RC == &X86::RFP80RegClass) {
Opc = X86::ST_FpP80m; // pops
} else if (RC == &X86::RFP64RegClass) {
Opc = X86::ST_Fp64m;
} else if (RC == &X86::RFP32RegClass) {
Opc = X86::ST_Fp32m;
} else if (RC == &X86::FR32RegClass) {
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
} else if (RC == &X86::VR128RegClass) {
// FIXME: Use movaps once we are capable of selectively
// aligning functions that spill SSE registers on 16-byte boundaries.
Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64mr;
} else {
assert(0 && "Unknown regclass");
abort();
}
return Opc;
}
const TargetRegisterClass *
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
if (RC == &X86::CCRRegClass)
@ -790,7 +728,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
while (MBBI != MBB.begin()) {
MachineBasicBlock::iterator PI = prior(MBBI);
unsigned Opc = PI->getOpcode();
if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
if (Opc != X86::POP32r && Opc != X86::POP64r &&
!PI->getDesc()->isTerminator())
break;
--MBBI;
}