diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index df153034610..9c121e56a84 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3669,9 +3669,10 @@ void MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset, unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { // As described by the Mips32r2 spec, the registers Rd and Rs for // jalr.hb must be different. + // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction unsigned Opcode = Inst.getOpcode(); - if (Opcode == Mips::JALR_HB && + if ((Opcode == Mips::JALR_HB || Opcode == Mips::JALRC_HB_MMR6) && (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())) return Match_RequiresDifferentSrcAndDst; diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 4f65d4e78f7..37e9d91cc37 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -494,6 +494,20 @@ class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6 funct> let Inst{15-0} = offset; } +class POOL32A_JALRC_FM_MMR6 funct> + : MipsR6Inst, MMR6Arch { + bits<5> rt; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} + class POOL32A_ERET_FM_MMR6 funct> : MMR6Arch { bits<32> Inst; @@ -984,3 +998,15 @@ class CMP_BRANCH_2R_OFF16_FM_MMR6 funct> let Inst{15-0} = offset; } +class POOL32A_DVPEVP_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = 0b00000; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 02ee85f529d..d0c108c940a 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -164,6 +164,7 @@ class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>; class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; +class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>; class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; @@ -200,6 +201,8 @@ class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; +class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>; +class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>; class CMP_CBR_RT_Z_MMR6_DESC_BASE @@ -1133,6 +1136,17 @@ class SWSP_MMR6_DESC let mayStore = 1; } +class JALRC_HB_MMR6_DESC { + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins GPR32Opnd:$rs); + string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs"); + list Pattern = []; + InstrItinClass Itinerary = NoItinerary; + Format Form = FrmJ; + bit isIndirectBranch = 1; + bit hasDelaySlot = 0; +} + class TLBINV_MMR6_DESC_BASE { dag OutOperandList = (outs); dag InOperandList = (ins); @@ -1143,6 +1157,16 @@ class TLBINV_MMR6_DESC_BASE { class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; +class DVPEVP_MMR6_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins GPR32Opnd:$rs); + string AsmString = !strconcat(opstr, "\t$rs"); + list Pattern = []; +} + +class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">; +class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -1417,6 +1441,8 @@ def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC, ISA_MICROMIPS32R6; def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, ISA_MICROMIPS32R6; +def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, + ISA_MICROMIPS32R6; def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC, ISA_MICROMIPS32R6; def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1449,6 +1475,8 @@ def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC, ISA_MICROMIPS32R6; def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, ISA_MICROMIPS32R6; +def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6; +def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6; } def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1496,6 +1524,10 @@ def : MipsInstAlias<"mfc0 $rt, $rs", def : MipsInstAlias<"mfhc0 $rt, $rs", (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // diff --git a/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 955dc4d2ab1..feaf26dce90 100644 --- a/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -302,3 +302,9 @@ 0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x33 0x7c # CHECK: tlbwr +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 diff --git a/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/test/MC/Disassembler/Mips/micromips64r6/valid.txt index e5aef3266a1..f53747878a1 100644 --- a/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -230,3 +230,9 @@ 0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x33 0x7c # CHECK: tlbwr +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s index 24e5a14d60c..1cbf251c0f0 100644 --- a/test/MC/Mips/micromips32r6/invalid.s +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -149,3 +149,9 @@ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 63ec604d578..5223e9abdc0 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -313,3 +313,9 @@ tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] diff --git a/test/MC/Mips/micromips64r6/invalid.s b/test/MC/Mips/micromips64r6/invalid.s index 42f31513429..c76f1d396fa 100644 --- a/test/MC/Mips/micromips64r6/invalid.s +++ b/test/MC/Mips/micromips64r6/invalid.s @@ -174,3 +174,9 @@ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different diff --git a/test/MC/Mips/micromips64r6/valid.s b/test/MC/Mips/micromips64r6/valid.s index 8ec7f8587dd..cf4eaf1308b 100644 --- a/test/MC/Mips/micromips64r6/valid.s +++ b/test/MC/Mips/micromips64r6/valid.s @@ -225,5 +225,11 @@ a: tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] 1: