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R600/SI: Add support for i64 bitwise or

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193213 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-10-23 00:44:19 +00:00
parent f9e5c39811
commit 6a2f9b9137
2 changed files with 36 additions and 4 deletions
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19
lib/Target/R600/SIInstructions.td
View File

@ -1962,6 +1962,25 @@ def : Pat<
(V_CMP_U_F32_e64 $src0, $src1)
>;
//============================================================================//
// Miscellaneous Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(i64 (trunc i128:$x)),
(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(i32 (EXTRACT_SUBREG $x, sub0)), sub0),
(i32 (EXTRACT_SUBREG $x, sub1)), sub1)
>;
def : Pat <
(or i64:$a, i64:$b),
(INSERT_SUBREG
(INSERT_SUBREG (IMPLICIT_DEF),
(V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0),
(V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1)
>;
//============================================================================//
// Miscellaneous Optimization Patterns
//============================================================================//

21
test/CodeGen/R600/or.ll
View File

@ -1,11 +1,11 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
; EG-CHECK: @or_v2i32
; EG-CHECK-LABEL: @or_v2i32
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
;SI-CHECK: @or_v2i32
;SI-CHECK-LABEL: @or_v2i32
;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
@ -18,13 +18,13 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in)
ret void
}
; EG-CHECK: @or_v4i32
; EG-CHECK-LABEL: @or_v4i32
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
;SI-CHECK: @or_v4i32
;SI-CHECK-LABEL: @or_v4i32
;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
@ -38,3 +38,16 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in)
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
}
; EG-CHECK-LABEL: @or_i64
; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[3].X
; SI-CHECK-LABEL: @or_i64
; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}}
; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}}
define void @or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
entry:
%0 = or i64 %a, %b
store i64 %0, i64 addrspace(1)* %out
ret void
}