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Various small changes related to the Condition Register on PowerPC.

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Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2009-07-03 06:47:55 +00:00
parent 2a9ddfb903
commit 6a3a1ba97e
4 changed files with 68 additions and 47 deletions
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31
lib/Target/PowerPC/PPCFrameInfo.h
View File

@ -139,21 +139,22 @@ public:
std::pair<unsigned, int>(PPC::R14, -72),
// CR save area offset.
std::pair<unsigned, int>(PPC::CR2, -4),
std::pair<unsigned, int>(PPC::CR3, -4),
std::pair<unsigned, int>(PPC::CR4, -4),
std::pair<unsigned, int>(PPC::CR2LT, -4),
std::pair<unsigned, int>(PPC::CR2GT, -4),
std::pair<unsigned, int>(PPC::CR2EQ, -4),
std::pair<unsigned, int>(PPC::CR2UN, -4),
std::pair<unsigned, int>(PPC::CR3LT, -4),
std::pair<unsigned, int>(PPC::CR3GT, -4),
std::pair<unsigned, int>(PPC::CR3EQ, -4),
std::pair<unsigned, int>(PPC::CR3UN, -4),
std::pair<unsigned, int>(PPC::CR4LT, -4),
std::pair<unsigned, int>(PPC::CR4GT, -4),
std::pair<unsigned, int>(PPC::CR4EQ, -4),
std::pair<unsigned, int>(PPC::CR4UN, -4),
// FIXME SVR4: Disable CR save area for now.
// std::pair<unsigned, int>(PPC::CR2, -4),
// std::pair<unsigned, int>(PPC::CR3, -4),
// std::pair<unsigned, int>(PPC::CR4, -4),
// std::pair<unsigned, int>(PPC::CR2LT, -4),
// std::pair<unsigned, int>(PPC::CR2GT, -4),
// std::pair<unsigned, int>(PPC::CR2EQ, -4),
// std::pair<unsigned, int>(PPC::CR2UN, -4),
// std::pair<unsigned, int>(PPC::CR3LT, -4),
// std::pair<unsigned, int>(PPC::CR3GT, -4),
// std::pair<unsigned, int>(PPC::CR3EQ, -4),
// std::pair<unsigned, int>(PPC::CR3UN, -4),
// std::pair<unsigned, int>(PPC::CR4LT, -4),
// std::pair<unsigned, int>(PPC::CR4GT, -4),
// std::pair<unsigned, int>(PPC::CR4EQ, -4),
// std::pair<unsigned, int>(PPC::CR4UN, -4),
// VRSAVE save area offset.
std::pair<unsigned, int>(PPC::VRSAVE, -4),

48
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -444,21 +444,29 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
// not cause any bug. If we need other uses of CR bits, the following
// code may be invalid.
unsigned Reg = 0;
if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
Reg = PPC::CR0;
else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
Reg = PPC::CR1;
else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
Reg = PPC::CR2;
else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
Reg = PPC::CR3;
else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
Reg = PPC::CR4;
else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
Reg = PPC::CR5;
else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
Reg = PPC::CR6;
else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
Reg = PPC::CR7;
return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
@ -587,21 +595,29 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
} else if (RC == PPC::CRBITRCRegisterClass) {
unsigned Reg = 0;
if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
Reg = PPC::CR0;
else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
Reg = PPC::CR1;
else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
Reg = PPC::CR2;
else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
Reg = PPC::CR3;
else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
Reg = PPC::CR4;
else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
Reg = PPC::CR5;
else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
Reg = PPC::CR6;
else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
Reg = PPC::CR7;
return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,

5
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -1049,9 +1049,10 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
if (Reg < MinFPR) {
MinFPR = Reg;
}
} else if ( RC == PPC::CRBITRCRegisterClass
// FIXME SVR4: Disable CR save area for now.
} else if ( RC == PPC::CRBITRCRegisterClass
|| RC == PPC::CRRCRegisterClass) {
HasCRSaveArea = true;
// HasCRSaveArea = true;
} else if (RC == PPC::VRSAVERCRegisterClass) {
HasVRSAVESaveArea = true;
} else if (RC == PPC::VRRCRegisterClass) {

31
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -43,8 +43,9 @@ class VR<bits<5> num, string n> : PPCReg<n> {
}
// CR - One of the 8 4-bit condition registers
class CR<bits<3> num, string n> : PPCReg<n> {
class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
field bits<3> Num = num;
let SubRegs = subregs;
}
// CRBIT - One of the 32 1-bit condition register fields
@ -189,16 +190,6 @@ def V29 : VR<29, "v29">, DwarfRegNum<[106]>;
def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
// Condition registers
def CR0 : CR<0, "cr0">, DwarfRegNum<[68]>;
def CR1 : CR<1, "cr1">, DwarfRegNum<[69]>;
def CR2 : CR<2, "cr2">, DwarfRegNum<[70]>;
def CR3 : CR<3, "cr3">, DwarfRegNum<[71]>;
def CR4 : CR<4, "cr4">, DwarfRegNum<[72]>;
def CR5 : CR<5, "cr5">, DwarfRegNum<[73]>;
def CR6 : CR<6, "cr6">, DwarfRegNum<[74]>;
def CR7 : CR<7, "cr7">, DwarfRegNum<[75]>;
// Condition register bits
def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>;
def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>;
@ -233,6 +224,16 @@ def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>;
def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>;
def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
// Condition registers
def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>;
def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>;
def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>;
def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>;
def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>;
def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>;
def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
[CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
@ -348,9 +349,6 @@ def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
V29, V28, V27, V26, V25, V24, V23, V22, V21, V20]>;
def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
CR3, CR4]>;
def CRBITRC : RegisterClass<"PPC", [i32], 32,
[CR0LT, CR0GT, CR0EQ, CR0UN,
CR1LT, CR1GT, CR1EQ, CR1UN,
@ -365,6 +363,11 @@ def CRBITRC : RegisterClass<"PPC", [i32], 32,
let CopyCost = -1;
}
def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
CR3, CR4]>
{
let SubRegClassList = [CRBITRC, CRBITRC, CRBITRC, CRBITRC];
}
def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;