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[mips] Refactor jump, jump register, jump-and-link and nop instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
0a57dc1d14
commit
6a8309e62a
@ -164,7 +164,7 @@ let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
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}
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/// Jump and Branch Instructions
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def JR64 : IndirectBranch<CPU64Regs>;
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def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
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@ -173,8 +173,8 @@ def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
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}
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let DecoderNamespace = "Mips64" in
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def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall;
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def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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/// Multiply and Divide Instructions.
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@ -163,14 +163,14 @@ class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
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// Format J instruction class in Mips : <|opcode|address|>
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//===----------------------------------------------------------------------===//
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class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
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class FJ<bits<6> op>
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{
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bits<26> addr;
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bits<26> target;
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let Opcode = op;
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bits<32> Inst;
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let Inst{25-0} = addr;
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let Inst{31-26} = op;
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let Inst{25-0} = target;
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}
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//===----------------------------------------------------------------------===//
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@ -368,6 +368,25 @@ class LUI_FM {
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let Inst{15-0} = imm16;
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}
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class NOP_FM {
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bits<32> Inst;
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let Inst{31-0} = 0;
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}
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class JALR_FM {
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = 31;
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let Inst{10-6} = 0;
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let Inst{5-0} = 9;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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@ -506,10 +506,10 @@ class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
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[(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
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// Jump
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class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
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SDPatternOperator operator, SDPatternOperator targetoperator>:
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FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
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[(operator targetoperator:$target)], IIBranch> {
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class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
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SDPatternOperator targetoperator> :
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InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
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[(operator targetoperator:$target)], IIBranch, FrmJ> {
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let isTerminator=1;
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let isBarrier=1;
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let hasDelaySlot = 1;
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@ -532,11 +532,7 @@ class UncondBranch<string opstr> :
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// Base class for indirect branch and return instruction classes.
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let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
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FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
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let rt = 0;
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let rd = 0;
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let shamt = 0;
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}
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InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
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// Indirect branch
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class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
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@ -554,22 +550,16 @@ class RetBase<RegisterClass RC>: JumpFR<RC> {
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1, Defs = [RA] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ<op, (outs), (ins calltarget:$target),
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!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
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IIBranch> {
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let DecoderMethod = "DecodeJumpTarget";
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}
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
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RegisterClass RC>:
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FR<op, func, (outs), (ins RC:$rs),
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!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
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let rt = 0;
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let rd = 31;
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let shamt = 0;
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class JumpLink<string opstr> :
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InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
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[(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
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let DecoderMethod = "DecodeJumpTarget";
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}
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class JumpLinkReg<string opstr, RegisterClass RC>:
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InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"),
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[(MipsJmpLink RC:$rs)], IIBranch, FrmR>;
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class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
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FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
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!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
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@ -858,9 +848,9 @@ let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
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}
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/// Jump and Branch Instructions
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def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
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def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
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Requires<[RelocStatic, HasStdEnc]>, IsBranch;
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def JR : IndirectBranch<CPURegs>;
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def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
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def B : UncondBranch<"b">, B_FM;
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def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
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def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
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@ -873,14 +863,14 @@ let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
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hasDelaySlot = 1, Defs = [RA] in
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def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
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def JAL : JumpLink<"jal">, FJ<3>;
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def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
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def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
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def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
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def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
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def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
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def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
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def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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def RET : RetBase<CPURegs>;
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def RET : RetBase<CPURegs>, MTLO_FM<8>;
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/// Multiply and Divide Instructions.
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def MULT : Mult32<0x18, "mult", IIImul>;
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@ -904,9 +894,9 @@ def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>;
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/// Word Swap Bytes Within Halfwords
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def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
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/// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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/// No operation.
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/// FIXME: NOP should be an alias of "sll $0, $0, 0".
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def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM;
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// FrameIndexes are legalized when they are operands from load/store
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// instructions. The same not happens for stack address copies, so an
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