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Target/R600: Update MIB according to r170588.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
NAKAMURA Takumi 2012-12-20 00:22:11 +00:00
parent 6d1fc5389f
commit 6b207d3cfa
3 changed files with 29 additions and 22 deletions
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34
lib/Target/R600/AMDILCFGStructurizer.cpp
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@ -2022,7 +2022,9 @@ CFGStructurizer<PassT>::normalizeInfiniteLoopExit(LoopT* LoopRep) {
CFGTraits::insertAssignInstrBefore(insertPos, passRep, immReg, 1); CFGTraits::insertAssignInstrBefore(insertPos, passRep, immReg, 1);
InstrT *newInstr = InstrT *newInstr =
CFGTraits::insertInstrBefore(insertPos, AMDGPU::BRANCH_COND_i32, passRep); CFGTraits::insertInstrBefore(insertPos, AMDGPU::BRANCH_COND_i32, passRep);
MachineInstrBuilder(newInstr).addMBB(loopHeader).addReg(immReg, false); MachineInstrBuilder MIB(*funcRep, newInstr);
MIB.addMBB(loopHeader);
MIB.addReg(immReg, false);
SHOWNEWINSTR(newInstr); SHOWNEWINSTR(newInstr);
@ -2844,13 +2846,12 @@ struct CFGStructTraits<AMDGPUCFGStructurizer> {
MachineInstr *oldInstr = &(*instrPos); MachineInstr *oldInstr = &(*instrPos);
const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineBasicBlock *blk = oldInstr->getParent(); MachineBasicBlock *blk = oldInstr->getParent();
MachineInstr *newInstr = MachineFunction *MF = blk->getParent();
blk->getParent()->CreateMachineInstr(tii->get(newOpcode), MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL);
DL);
blk->insert(instrPos, newInstr); blk->insert(instrPos, newInstr);
MachineInstrBuilder(newInstr).addReg(oldInstr->getOperand(1).getReg(), MachineInstrBuilder MIB(*MF, newInstr);
false); MIB.addReg(oldInstr->getOperand(1).getReg(), false);
SHOWNEWINSTR(newInstr); SHOWNEWINSTR(newInstr);
//erase later oldInstr->eraseFromParent(); //erase later oldInstr->eraseFromParent();
@ -2863,13 +2864,13 @@ struct CFGStructTraits<AMDGPUCFGStructurizer> {
RegiT regNum, RegiT regNum,
DebugLoc DL) { DebugLoc DL) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineFunction *MF = blk->getParent();
MachineInstr *newInstr = MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL);
blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL);
//insert before //insert before
blk->insert(insertPos, newInstr); blk->insert(insertPos, newInstr);
MachineInstrBuilder(newInstr).addReg(regNum, false); MachineInstrBuilder(*MF, newInstr).addReg(regNum, false);
SHOWNEWINSTR(newInstr); SHOWNEWINSTR(newInstr);
} //insertCondBranchBefore } //insertCondBranchBefore
@ -2879,11 +2880,12 @@ struct CFGStructTraits<AMDGPUCFGStructurizer> {
AMDGPUCFGStructurizer *passRep, AMDGPUCFGStructurizer *passRep,
RegiT regNum) { RegiT regNum) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineFunction *MF = blk->getParent();
MachineInstr *newInstr = MachineInstr *newInstr =
blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DebugLoc()); MF->CreateMachineInstr(tii->get(newOpcode), DebugLoc());
blk->push_back(newInstr); blk->push_back(newInstr);
MachineInstrBuilder(newInstr).addReg(regNum, false); MachineInstrBuilder(*MF, newInstr).addReg(regNum, false);
SHOWNEWINSTR(newInstr); SHOWNEWINSTR(newInstr);
} //insertCondBranchEnd } //insertCondBranchEnd
@ -2928,12 +2930,14 @@ struct CFGStructTraits<AMDGPUCFGStructurizer> {
RegiT src2Reg) { RegiT src2Reg) {
const AMDGPUInstrInfo *tii = const AMDGPUInstrInfo *tii =
static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo()); static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo());
MachineFunction *MF = blk->getParent();
MachineInstr *newInstr = MachineInstr *newInstr =
blk->getParent()->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc()); MF->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc());
MachineInstrBuilder(newInstr).addReg(dstReg, RegState::Define); //set target MachineInstrBuilder MIB(*MF, newInstr);
MachineInstrBuilder(newInstr).addReg(src1Reg); //set src value MIB.addReg(dstReg, RegState::Define); //set target
MachineInstrBuilder(newInstr).addReg(src2Reg); //set src value MIB.addReg(src1Reg); //set src value
MIB.addReg(src2Reg); //set src value
blk->insert(instrPos, newInstr); blk->insert(instrPos, newInstr);
SHOWNEWINSTR(newInstr); SHOWNEWINSTR(newInstr);

12
lib/Target/R600/R600InstrInfo.cpp
View File

@ -72,10 +72,11 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF, MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
unsigned DstReg, int64_t Imm) const { unsigned DstReg, int64_t Imm) const {
MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); MachineInstrBuilder MIB(*MF, MI);
MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); MIB.addReg(DstReg, RegState::Define);
MachineInstrBuilder(MI).addImm(Imm); MIB.addReg(AMDGPU::ALU_LITERAL_X);
MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT MIB.addImm(Imm);
MIB.addReg(0); // PREDICATE_BIT
return MI; return MI;
} }
@ -449,7 +450,8 @@ R600InstrInfo::PredicateInstruction(MachineInstr *MI,
if (PIdx != -1) { if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx); MachineOperand &PMO = MI->getOperand(PIdx);
PMO.setReg(Pred[2].getReg()); PMO.setReg(Pred[2].getReg());
MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
return true; return true;
} }

5
lib/Target/R600/SIInstrInfo.cpp
View File

@ -62,8 +62,9 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const { int64_t Imm) const {
MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); MachineInstrBuilder MIB(*MF, MI);
MachineInstrBuilder(MI).addImm(Imm); MIB.addReg(DstReg, RegState::Define);
MIB.addImm(Imm);
return MI; return MI;