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Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-05-03 07:12:59 +00:00
parent d99d68bcee
commit 6b28d356c5
3 changed files with 37 additions and 22 deletions
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6
lib/Target/X86/Utils/X86ShuffleDecode.cpp
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@ -82,8 +82,7 @@ void DecodePSHUFMask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
void DecodePSHUFHWMask(EVT VT, unsigned Imm,
SmallVectorImpl<int> &ShuffleMask) {
unsigned NumLanes = VT.getSizeInBits() / 128;
unsigned NumElts = 8 * NumLanes;
unsigned NumElts = VT.getVectorNumElements();
for (unsigned l = 0; l != NumElts; l += 8) {
unsigned NewImm = Imm;
@ -99,8 +98,7 @@ void DecodePSHUFHWMask(EVT VT, unsigned Imm,
void DecodePSHUFLWMask(EVT VT, unsigned Imm,
SmallVectorImpl<int> &ShuffleMask) {
unsigned NumLanes = VT.getSizeInBits() / 128;
unsigned NumElts = 8 * NumLanes;
unsigned NumElts = VT.getVectorNumElements();
for (unsigned l = 0; l != NumElts; l += 8) {
unsigned NewImm = Imm;

51
lib/Target/X86/X86ISelLowering.cpp
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@ -3904,9 +3904,8 @@ static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
for (unsigned i = 0; i != NumElts; ++i) {
int Elt = N->getMaskElt(i);
if (Elt < 0) continue;
Elt %= NumLaneElts;
unsigned ShAmt = i << Shift;
if (ShAmt >= 8) ShAmt -= 8;
Elt &= NumLaneElts - 1;
unsigned ShAmt = (i << Shift) % 8;
Mask |= Elt << ShAmt;
}
@ -3916,30 +3915,48 @@ static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
EVT VT = N->getValueType(0);
assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
"Unsupported vector type for PSHUFHW");
unsigned NumElts = VT.getVectorNumElements();
unsigned Mask = 0;
// 8 nodes, but we only care about the last 4.
for (unsigned i = 7; i >= 4; --i) {
int Val = N->getMaskElt(i);
if (Val >= 0)
Mask |= (Val - 4);
if (i != 4)
Mask <<= 2;
for (unsigned l = 0; l != NumElts; l += 8) {
// 8 nodes per lane, but we only care about the last 4.
for (unsigned i = 0; i < 4; ++i) {
int Elt = N->getMaskElt(l+i+4);
if (Elt < 0) continue;
Elt &= 0x3; // only 2-bits.
Mask |= Elt << (i * 2);
}
}
return Mask;
}
/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
EVT VT = N->getValueType(0);
assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
"Unsupported vector type for PSHUFHW");
unsigned NumElts = VT.getVectorNumElements();
unsigned Mask = 0;
// 8 nodes, but we only care about the first 4.
for (int i = 3; i >= 0; --i) {
int Val = N->getMaskElt(i);
if (Val >= 0)
Mask |= Val;
if (i != 0)
Mask <<= 2;
for (unsigned l = 0; l != NumElts; l += 8) {
// 8 nodes per lane, but we only care about the first 4.
for (unsigned i = 0; i < 4; ++i) {
int Elt = N->getMaskElt(l+i);
if (Elt < 0) continue;
Elt &= 0x3; // only 2-bits
Mask |= Elt << (i * 2);
}
}
return Mask;
}

2
test/CodeGen/X86/avx2-shuffle.ll
View File

@ -23,6 +23,6 @@ entry:
; CHECK: vpshuflw $27, %ymm
define <16 x i16> @vpshuflw(<16 x i16> %src1) nounwind uwtable readnone ssp {
entry:
%shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15>
%shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> <i32 3, i32 undef, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15>
ret <16 x i16> %shuffle.i
}