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MachineScheduler: Skip acyclic latency heuristic for in-order cores

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The current heuristic is triggered on `InFlightCount > BufferLimit`
which isn't really helpful on in-order cores where BufferLimit is zero.

Note that we already get latency hiding effects for in order cores
by instructions staying in the pending queue on stalls; The additional
latency scheduling heuristics only have minimal effects after that while
occasionally increasing register pressure too much resulting in extra
spills.

My motivation here is additional spills/reloads ending up in a loop in
464.h264ref / BlockMotionSearch function resulting in a 4% overal
regression on an in order core. rdar://30264380

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300083 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2017-04-12 18:09:05 +00:00
parent c7bad98e0e
commit 6b814345d1
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/MachineScheduler.cpp
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@ -2729,7 +2729,7 @@ void GenericScheduler::registerRoots() {
errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
}
if (EnableCyclicPath) {
if (EnableCyclicPath && SchedModel->getMicroOpBufferSize() > 0) {
Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
checkAcyclicLatency();
}