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[PowerPC] Fix v2f64 vector extract and related patterns

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First, v2f64 vector extract had not been declared legal (and so the existing
patterns were not being used). Second, the patterns for that, and for
scalar_to_vector, should really be a regclass copy, not a subregister
operation, because the VSX registers directly hold both the vector and scalar data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-03-27 22:22:48 +00:00
parent 72f0f26d3b
commit 6bdc4ebedd
3 changed files with 22 additions and 4 deletions
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1
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -535,6 +535,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
if (Subtarget->hasVSX()) {
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);

7
lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -724,13 +724,12 @@ def : InstAlias<"xxswapd $XT, $XB",
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
def : Pat<(v2f64 (scalar_to_vector f64:$A)),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), $A, sub_64)>;
(v2f64 (COPY_TO_REGCLASS $A, VSRC))>;
def : Pat<(f64 (vector_extract v2f64:$S, 0)),
(EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS $S, VSLRC)), sub_64)>;
(f64 (COPY_TO_REGCLASS $S, VSRC))>;
def : Pat<(f64 (vector_extract v2f64:$S, 1)),
(EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 3),
VSLRC)), sub_64)>;
(f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSRC))>;
// Additional fnmsub patterns: -a*c + b == -(a*c - b)
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),

18
test/CodeGen/PowerPC/vsx.ll
View File

@ -529,3 +529,21 @@ define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
; CHECK: blr
}
define double @test63(<2 x double> %a) {
%v = extractelement <2 x double> %a, i32 0
ret double %v
; CHECK-LABEL: @test63
; CHECK: xxlor 1, 34, 34
; CHECK: blr
}
define double @test64(<2 x double> %a) {
%v = extractelement <2 x double> %a, i32 1
ret double %v
; CHECK-LABEL: @test64
; CHECK: xxpermdi 1, 34, 34, 2
; CHECK: blr
}