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Support for comi / ucomi intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27444 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
a43622683f
commit
6be2c58c8c
@ -19,6 +19,7 @@
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -323,6 +324,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
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}
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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computeRegisterProperties();
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// FIXME: These should be based on subtarget info. Plus, the values should
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@ -1185,9 +1189,8 @@ static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
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/// specific condition code. It returns a false if it cannot do a direct
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/// translation. X86CC is the translated CondCode. Flip is set to true if the
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/// the order of comparison operands should be flipped.
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static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
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bool &Flip) {
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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unsigned &X86CC, bool &Flip) {
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Flip = false;
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X86CC = X86ISD::COND_INVALID;
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if (!isFP) {
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@ -1237,6 +1240,11 @@ static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
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return X86CC != X86ISD::COND_INVALID;
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}
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static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
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bool &Flip) {
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return translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, Flip);
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}
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/// hasFPCMov - is there a floating point cmov for the specific X86 condition
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/// code. Current x86 isa includes the following FP cmov instructions:
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/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
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@ -2146,7 +2154,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// If the X86ISD::SETCC has more than one use, then it's probably better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason).
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if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
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unsigned CmpOpc = Op0.getOperand(1).getOpcode();
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if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
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CmpOpc == X86ISD::UCOMI) {
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if (!Op0.hasOneUse()) {
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std::vector<MVT::ValueType> Tys;
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for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
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@ -2160,7 +2170,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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CC = Op0.getOperand(0);
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Cond = Op0.getOperand(1);
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// Make a copy as flag result cannot be used by more than one.
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Cond = DAG.getNode(CmpOpc, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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addTest =
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isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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@ -2201,7 +2211,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// If the X86ISD::SETCC has more than one use, then it's probably better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason).
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if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
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unsigned CmpOpc = Cond.getOperand(1).getOpcode();
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if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
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CmpOpc == X86ISD::UCOMI) {
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if (!Cond.hasOneUse()) {
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std::vector<MVT::ValueType> Tys;
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for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
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@ -2215,7 +2227,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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// Make a copy as flag result cannot be used by more than one.
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Cond = DAG.getNode(CmpOpc, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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} else
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addTest = true;
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@ -2829,6 +2841,111 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return SDOperand();
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
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switch (IntNo) {
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default: return SDOperand(); // Don't custom lower most intrinsics.
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// Comparison intrinsics.
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case Intrinsic::x86_sse_comieq_ss:
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case Intrinsic::x86_sse_comilt_ss:
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case Intrinsic::x86_sse_comile_ss:
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case Intrinsic::x86_sse_comigt_ss:
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case Intrinsic::x86_sse_comige_ss:
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case Intrinsic::x86_sse_comineq_ss:
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case Intrinsic::x86_sse_ucomieq_ss:
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case Intrinsic::x86_sse_ucomilt_ss:
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case Intrinsic::x86_sse_ucomile_ss:
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case Intrinsic::x86_sse_ucomigt_ss:
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case Intrinsic::x86_sse_ucomige_ss:
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case Intrinsic::x86_sse_ucomineq_ss:
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case Intrinsic::x86_sse2_comieq_sd:
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case Intrinsic::x86_sse2_comilt_sd:
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case Intrinsic::x86_sse2_comile_sd:
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case Intrinsic::x86_sse2_comigt_sd:
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case Intrinsic::x86_sse2_comige_sd:
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case Intrinsic::x86_sse2_comineq_sd:
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case Intrinsic::x86_sse2_ucomieq_sd:
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case Intrinsic::x86_sse2_ucomilt_sd:
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case Intrinsic::x86_sse2_ucomile_sd:
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case Intrinsic::x86_sse2_ucomigt_sd:
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case Intrinsic::x86_sse2_ucomige_sd:
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case Intrinsic::x86_sse2_ucomineq_sd: {
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unsigned Opc;
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ISD::CondCode CC;
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switch (IntNo) {
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default: break;
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case Intrinsic::x86_sse_comieq_ss:
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case Intrinsic::x86_sse2_comieq_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETEQ;
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break;
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case Intrinsic::x86_sse_comilt_ss:
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case Intrinsic::x86_sse2_comilt_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETLT;
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break;
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case Intrinsic::x86_sse_comile_ss:
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case Intrinsic::x86_sse2_comile_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETLE;
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break;
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case Intrinsic::x86_sse_comigt_ss:
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case Intrinsic::x86_sse2_comigt_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETGT;
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break;
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case Intrinsic::x86_sse_comige_ss:
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case Intrinsic::x86_sse2_comige_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETGE;
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break;
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case Intrinsic::x86_sse_comineq_ss:
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case Intrinsic::x86_sse2_comineq_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETNE;
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break;
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case Intrinsic::x86_sse_ucomieq_ss:
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case Intrinsic::x86_sse2_ucomieq_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETEQ;
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break;
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case Intrinsic::x86_sse_ucomilt_ss:
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case Intrinsic::x86_sse2_ucomilt_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETLT;
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break;
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case Intrinsic::x86_sse_ucomile_ss:
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case Intrinsic::x86_sse2_ucomile_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETLE;
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break;
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case Intrinsic::x86_sse_ucomigt_ss:
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case Intrinsic::x86_sse2_ucomigt_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETGT;
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break;
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case Intrinsic::x86_sse_ucomige_ss:
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case Intrinsic::x86_sse2_ucomige_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETGE;
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break;
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case Intrinsic::x86_sse_ucomineq_ss:
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case Intrinsic::x86_sse2_ucomineq_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETNE;
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break;
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}
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bool Flip;
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unsigned X86CC;
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translateX86CC(CC, true, X86CC, Flip);
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SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1),
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Op.getOperand(Flip?1:2));
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SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
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}
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}
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}
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}
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}
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@ -2853,6 +2970,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::TEST: return "X86ISD::TEST";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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case X86ISD::SETCC: return "X86ISD::SETCC";
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case X86ISD::CMOV: return "X86ISD::CMOV";
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case X86ISD::BRCOND: return "X86ISD::BRCOND";
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@ -106,7 +106,7 @@ namespace llvm {
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, TEST,
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CMP, TEST, COMI, UCOMI,
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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@ -19,10 +19,14 @@
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
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[SDNPOutFlag]>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
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[SDNPOutFlag]>;
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def X86s2vec : SDNode<"X86ISD::S2VEC",
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SDTypeProfile<1, 1, []>, []>;
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def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
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@ -559,6 +563,31 @@ def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>;
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}
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def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
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def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
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def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
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def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
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def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
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"comiss {$src2, $src1|$src1, $src2}",
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[(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
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def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
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"comiss {$src2, $src1|$src1, $src2}",
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[(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
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def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
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"comisd {$src2, $src1|$src1, $src2}",
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[(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
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def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
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"comisd {$src2, $src1|$src1, $src2}",
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[(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
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// Aliases of packed instructions for scalar use. These all have names that
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// start with 'Fs'.
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