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Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms.
This allows the 64-bit forms to use+def RSP instead of ESP. This doesn't fix any real bugs today, but it is more precise and it makes the debug dumps on x86-64 look more consistent. Also, add some comments describing the CALL instructions' physreg operand uses and defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56925 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -960,7 +960,8 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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unsigned NumBytes = CCInfo.getNextStackOffset();
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// Issue CALLSEQ_START
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BuildMI(MBB, TII.get(X86::ADJCALLSTACKDOWN)).addImm(NumBytes);
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unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
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BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
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// Process argumenet: walk the register/memloc assignments, inserting
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// copies / loads.
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@ -1051,7 +1052,8 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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}
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// Issue CALLSEQ_END
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BuildMI(MBB, TII.get(X86::ADJCALLSTACKUP)).addImm(NumBytes).addImm(0);
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unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
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BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
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// Now handle call return value (if any).
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if (RetVT.getSimpleVT() != MVT::isVoid) {
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@ -86,11 +86,30 @@ def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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// Instruction list...
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//
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start imm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end imm:$amt1, imm:$amt2)]>,
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Requires<[In64BitMode]>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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@ -321,12 +321,14 @@ def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [ESP, EFLAGS], Uses = [ESP] in {
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def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end imm:$amt1, imm:$amt2)]>;
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def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start imm:$amt)]>,
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Requires<[In32BitMode]>;
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def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end imm:$amt1, imm:$amt2)]>,
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Requires<[In32BitMode]>;
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}
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// Nop
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@ -411,7 +413,10 @@ def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS],
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@ -42,7 +42,12 @@ using namespace llvm;
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X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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const TargetInstrInfo &tii)
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: X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
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: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKDOWN64 :
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X86::ADJCALLSTACKDOWN32,
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tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKUP64 :
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X86::ADJCALLSTACKUP32),
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TM(tm), TII(tii) {
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// Cache some information.
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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@ -367,11 +372,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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MachineInstr *New = 0;
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if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
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if (Old->getOpcode() == getCallFrameSetupOpcode()) {
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New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
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StackPtr).addReg(StackPtr).addImm(Amount);
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} else {
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assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
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assert(Old->getOpcode() == getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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uint64_t CalleeAmt = Old->getOperand(1).getImm();
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Amount -= CalleeAmt;
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@ -387,7 +392,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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// Replace the pseudo instruction with a new instruction...
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if (New) MBB.insert(I, New);
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}
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} else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
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} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back. We do this until we have
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// more advanced stack pointer tracking ability.
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