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MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.

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rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-01 23:15:50 +00:00
parent 857b1939da
commit 6da3fe68c6
2 changed files with 18 additions and 0 deletions
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1
lib/Target/ARM/ARMInstrInfo.td
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@ -2009,6 +2009,7 @@ def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
bits<4> Rd;
bits<12> src;
let Inst{15-12} = Rd;
let Inst{19-16} = 0b0000;
let Inst{11-0} = src;
let Inst{25} = 0;
}

17
test/MC/Disassembler/ARM/invalid-MOVs-arm.txt Normal file
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@ -0,0 +1,17 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
# The instruction is UNPREDICTABLE, and is not a valid intruction.
#
# See also
# A8.6.88 LSL (immediate)
# A8.6.98 MOV (shifted register), and
# I.1 Instruction encoding diagrams and pseudocode
0x2 0xd1 0xbc 0xf1