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Make sub- super- reg-class tables static.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29190 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-07-18 22:18:31 +00:00
parent 21ba23d0d8
commit 6f6602ce42
1 changed files with 6 additions and 3 deletions
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9
utils/TableGen/RegisterInfoEmitter.cpp
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@ -127,7 +127,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
std::string Name = RC.TheDef->getName();
// Emit the register list now.
OS << " // " << Name << " Register Class...\n const unsigned " << Name
OS << " // " << Name << " Register Class...\n"
<< " static const unsigned " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
Record *Reg = RC.Elements[i];
@ -180,7 +181,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
}
OS << " // " << Name
<< " Register Class sub-classes...\n const TargetRegisterClass* "
<< " Register Class sub-classes...\n"
<< " static const TargetRegisterClass* "
<< Name << "Subclasses [] = {\n ";
bool Empty = true;
@ -214,7 +216,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
std::string Name = RC.TheDef->getName();
OS << " // " << Name
<< " Register Class super-classes...\n const TargetRegisterClass* "
<< " Register Class super-classes...\n"
<< " static const TargetRegisterClass* "
<< Name << "Superclasses [] = {\n ";
bool Empty = true;