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now that generic vector types aren't selected onto MMX registers, these

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tests don't need -disable-mmx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122188 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-19 20:12:58 +00:00
parent e019ec168b
commit 6f948be128
38 changed files with 36 additions and 38 deletions
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2
test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx -enable-legalize-types-checking
; RUN: llc < %s -march=x86 -mattr=+sse2 -enable-legalize-types-checking
declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone

2
test/CodeGen/X86/2009-07-07-SplitICmp.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -disable-mmx
; RUN: llc < %s -march=x86
define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
%D = icmp sgt <2 x i32> %A, %B

2
test/CodeGen/X86/bc-extract.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
define float @extractFloat1() nounwind {

2
test/CodeGen/X86/dagcombine-buildvector.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s
; Shows a dag combine bug that will generate an illegal build vector
; with v2i64 build_vector i32, i32.

2
test/CodeGen/X86/insertelement-legalize.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -disable-mmx
; RUN: llc < %s -march=x86
; Test to check that we properly legalize an insert vector element
define void @test(<2 x i64> %val, <2 x i64>* %dst, i64 %x) nounwind {

2
test/CodeGen/X86/legalizedag_vec.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=sse2 | FileCheck %s
; Test case for r63760 where we generate a legalization assert that an illegal

2
test/CodeGen/X86/scalar_widen_div.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -disable-mmx -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; Verify when widening a divide/remainder operation, we only generate a
; divide/rem per element since divide/remainder can trap.

2
test/CodeGen/X86/vec-trunc-store.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -disable-mmx >/dev/null
; RUN: llc < %s -march=x86-64
define void @foo(<8 x i32>* %p) nounwind {
%t = load <8 x i32>* %p

1
test/CodeGen/X86/vec_cast.ll
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@ -1,5 +1,4 @@
; RUN: llc < %s -march=x86-64 -mcpu=core2
; RUN: llc < %s -march=x86-64 -mcpu=core2 -disable-mmx
define <8 x i32> @a(<8 x i16> %a) nounwind {

2
test/CodeGen/X86/vec_compare-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s
declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone

1
test/CodeGen/X86/vec_ext_inreg.ll
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@ -1,5 +1,4 @@
; RUN: llc < %s -march=x86-64
; RUN: llc < %s -march=x86-64 -disable-mmx
define <8 x i32> @a(<8 x i32> %a) nounwind {
%b = trunc <8 x i32> %a to <8 x i16>

2
test/CodeGen/X86/vec_shuffle-30.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -disable-mmx -o %t
; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep pshufhw %t | grep -- -95 | count 1
; RUN: grep shufps %t | count 1
; RUN: not grep pslldq %t

2
test/CodeGen/X86/vshift-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.

2
test/CodeGen/X86/vshift-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.

2
test/CodeGen/X86/vshift-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.

2
test/CodeGen/X86/vshift-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same when using a shuffle splat.

2
test/CodeGen/X86/vshift-5.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; When loading the shift amount from memory, avoid generating the splat.

2
test/CodeGen/X86/vsplit-and.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 | FileCheck %s
define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {

2
test/CodeGen/X86/widen_arith-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; Widen a v3i8 to v16i8 to use a vector add

2
test/CodeGen/X86/widen_arith-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: paddb
; CHECK: pand

2
test/CodeGen/X86/widen_arith-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
; CHECK: paddw
; CHECK: pextrw
; CHECK: movd

2
test/CodeGen/X86/widen_arith-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; CHECK: psubw
; CHECK-NEXT: pmullw

2
test/CodeGen/X86/widen_arith-5.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; CHECK: movdqa
; CHECK: pmulld
; CHECK: psubd

2
test/CodeGen/X86/widen_arith-6.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: mulps
; CHECK: addps

2
test/CodeGen/X86/widen_cast-1.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=x86 -mattr=+sse42 < %s -disable-mmx | FileCheck %s
; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s
; CHECK: paddw
; CHECK: pextrd
; CHECK: movd

2
test/CodeGen/X86/widen_cast-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: pextrd
; CHECK: pextrd
; CHECK: movd

2
test/CodeGen/X86/widen_cast-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: paddd
; CHECK: pextrd
; CHECK: pextrd

2
test/CodeGen/X86/widen_cast-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: sarb
; CHECK: sarb
; CHECK: sarb

2
test/CodeGen/X86/widen_cast-5.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: movl
; CHECK: movd

2
test/CodeGen/X86/widen_cast-6.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse41 | FileCheck %s
; CHECK: movd
; Test bit convert that requires widening in the operand.

2
test/CodeGen/X86/widen_conv-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: pshufd
; CHECK: paddd

2
test/CodeGen/X86/widen_conv-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: movswl
; CHECK: movswl

2
test/CodeGen/X86/widen_conv-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: cvtsi2ss
; sign to float v2i16 to v2f32

2
test/CodeGen/X86/widen_conv-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: cvtsi2ss
; unsigned to float v7i16 to v7f32

2
test/CodeGen/X86/widen_extract-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; widen extract subvector
define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {

2
test/CodeGen/X86/widen_load-1.ll
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@ -1,4 +1,4 @@
; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -disable-mmx | FileCheck %s
; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
; PR4891
; This load should be before the call, not after.

2
test/CodeGen/X86/widen_load-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 | FileCheck %s
; Test based on pr5626 to load/store
;

2
test/CodeGen/X86/widen_shuffle-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; widening shuffle v3float and then a add
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {